Wojciech Jarzyna

Prof. Wojciech Jarzyna

Department of Electrical Drives and Machines, Lublin University of Technology, 20-618 Lublin, Poland
orcid

Research Focus & Metrics

Academic Career Length

32Years (1995-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 January 2019 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
AYApurv Kumar Yadav
Apurv Kumar Yadav
KGK. Gopakumar
K. Gopakumar
KRKrishna Raj R
Krishna Raj R
LULoganathan Umanand
Loganathan Umanand
SBSubhashish Bhattacharya
Subhashish Bhattacharya
Wojciech JarzynaWojciech Jarzyna
Wojciech Jarzyna

1 May 2011 in Communications in Nonlinear Science and Numerical Simulation
Verified
Journal Article
Closed access
JWJerzy Warminski
Jerzy Warminski
MBMarcin Bochenski
Marcin Bochenski
Wojciech JarzynaWojciech Jarzyna
Wojciech Jarzyna
PFPiotr Filipek
Piotr Filipek
MAMichal Augustyniak
Michal Augustyniak

6 February 2020 in IEEE Journal of Emerging and Selected Topics in Power Electronics
Verified
Journal Article
Closed access
MMMriganka GHOSH Ghosh Majumder
Mriganka GHOSH Ghosh Majumder
RRRakesh R
Rakesh R
KGK. Gopakumar
K. Gopakumar
LULoganathan Umanand
Loganathan Umanand
Kamal Al-HaddadKamal Al-Haddad
Kamal Al-Haddad
Wojciech JarzynaWojciech Jarzyna
Wojciech Jarzyna

5 December 2019 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
MMMriganka GHOSH Ghosh Majumder
Mriganka GHOSH Ghosh Majumder
RRR. Rakesh
R. Rakesh
MIMohammed Imthias
Mohammed Imthias
KGK. Gopakumar
K. Gopakumar
ULUmanand Loganathan
Umanand Loganathan
Wojciech JarzynaWojciech Jarzyna
Wojciech Jarzyna
In this paper, a method is proposed, for the first time, to increase the linear modulation range till full base speed irrespective of load power factor for a multilevel inverter fed induction motor (IM) drive. A 5-level inverter with a single DC source is used for the proposed scheme. Using this method, linear PWM operation of the inverter can be achieved till peak phase fundamental voltage of 0.637Vdc without exceeding machine phase voltage rating. This method eliminates all the lower order harmonics from machine phase voltage till the full speed range of operation. The proposed 5-level inverter scheme is realized by cascading a 2-Level inverter with a capacitor fed H-Bridge, feeding Open-End Induction Motor (OEIM) drive from one end and a capacitor fed 2-Level inverter from the other end. The proposed scheme uses Space Vector (SV) redundancy to balance all the capacitors during its operation. Operation of the proposed drive is analyzed extensively for normal 5- Level operation as well as during the extended modulation range. Experimental results for steady state and transient state operation are presented to validate the proposed scheme.

31 March 2022 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
TDTutan Debnath
Tutan Debnath
RRRakesh Resalayyan
Rakesh Resalayyan
MIMohammed Imthias
Mohammed Imthias
KGK. Gopakumar
K. Gopakumar
LULoganathan Umanand
Loganathan Umanand
Wojciech JarzynaWojciech Jarzyna
Wojciech Jarzyna
This article proposes a novel nine-level multilevel inverter topology with an instantaneous voltage balancing scheme of stacked dc-link capacitors for an induction motor (IM) drive application. Three neutral points (NPs, terminal joints of four series-connected capacitors) across a single dc-link are balanced instantaneously (within a sampling interval) by ensuring zero current at the NPs. The proper selection of pole voltage from the redundancies provides zero current at any NP during the pulsewidth modulation operation under a steady-state and transient operation. A five-level stacked inverter and three cascaded hybrid-bridge (CHB) inverter cells are used in each phase. Along with the balancing of dc-link capacitors, CHB capacitors’ voltage balancing is also achieved using the pole voltage redundancies at all modulation indexes for all power factor and load. It is also possible to increase more number of levels using more low-voltage switches, and a generalized form of the topology is presented. The concept is validated using a laboratory-developed nine-level inverter with a three-phase IM load, operated under “V/f” control. The detailed experimental results for the steady and transient condition, simulation studies for switching loss, and harmonic content in the phase voltage are also presented.