Visual querying is essential for interactively exploring massive trajectory data. However, the data uncertainty imposes profound challenges to fulfill advanced analytics requirements. On the one hand, many underlying data does not contain accurate geographic coordinates, e.g., positions of a mobile phone only refer to the regions (i.e., mobile cell stations) in which it resides, instead of accurate GPS coordinates. On the other hand, domain experts and general users prefer a natural way, such as using a natural language sentence, to access and analyze massive movement data. In this paper, we propose a visual analytics approach that can extract spatial-temporal constraints from a textual sentence and support an effective query method over uncertain mobile trajectory data. It is built up on encoding massive, spatially uncertain trajectories by the semantic information of the POIs and regions covered by them, and then storing the trajectory documents in text database with an effective indexing scheme. The visual interface facilitates query condition specification, situation-aware visualization, and semantic exploration of large trajectory data. Usage scenarios on real-world human mobility datasets demonstrate the effectiveness of our approach.
22 August 2023 in IEEE Transactions on Parallel and Distributed Systems
In recent years, neuromorphic processors are widely used in many scenarios, showing extreme energy efficiency over traditional architectures. However, almost all existing neuromorphic hardware are following the heterogeneous computing methodology without Instruction Set Architecture (ISA), leading to inflexibility in programming. In this paper, we first propose a RISC-V Neuromorphic Extension (RVNE) to enable fine-grained and flexible homogeneous programming for neuromorphic algorithms while utilizing SNN sparsity from different levels of granularity and computing flows. Based on RVNE, we next implement a neuromorphic micro-architecture that is tightly coupled to the CPU pipeline to accelerate neuromorphic computing. To demonstrate the proposed homogeneous neuromorphic architecture, we implement a prototype processor called NeuroRVcore based on RISC-V ISA and an open-source RISC-V core. The evaluation results show that RVNE achieves a 2.8 × −4.3 × reduction in code density compared with the general-purpose ISAs. Compared with the state-of-the-art neuromorphic processor, the proposed homogeneous computing reduces energy consumption by 3.4%−22.5% while enabling fine-grained and flexible homogeneous programming.
30 November 2023 in Journal of Computer Science and Technology
Clock domain crossing (CDC) is an important issue in integrated circuit (IC) design and verification. In this paper, We present the design of 5 types of CDC schemes in our developed SOC chip with multi working mode and ten clock domain, deeply describe an approach using assertion-based verification (ABV) to verify proper functionality for CDC signals. Taped sample chip tests show all CDC designs work right, and demonstrate that design and verification method are effective.
1 August 2022 in IEEE Computer Architecture Letters
Stride prediction is a nonignorable part of value prediction. Most hybrid predictors cannot eliminate this pattern. Existing stride predictors can handle the regular stride pattern, but it is hard to fit well with the interval stride pattern. To deal with it, we introduce the notion of Stride Equality Prediction (SEP), which predicts the stride feature of the current instruction is equal to that of the last committed same instruction. SEP can deal well with interval-style stride patterns, which always perform a constant stride during an interval, although there may be different endpoints and strides in different intervals. SEP predicts the value of stride equality instructions from the last committed occurrence of the same instruction and the number of the same instruction in the instruction window. Evaluation results show that SEP is effective in stride value prediction. It outperforms the Enhanced Stride predictor for 5.3% and state-of-art computational predictor Context-based Computational Value TAGE (CBC-VTAGE) for 1.5% on average. Moreover, by applying the SEP update condition, CBC-VTAGE can obtain performance gain without extra cost.