Production of high-aspect-ratio silicon (Si) nanowire-based anode for lithium ion batteries is challenging particularly in terms of controlling wire property and geometry to improve the battery performance. This report demonstrates tunable optimization of inductively coupled plasma reactive ion etching (ICP-RIE) at cryogenic temperature to fabricate vertically-aligned silicon nanowire array anodes with high verticality, controllable morphology, and good homogeneity. Three different materials [i.e., photoresist, chromium (Cr), and silicon dioxide (SiO₂)] were employed as masks during the subsequent photolithography and cryogenic ICP-RIE processes to investigate their effects on the resulting nanowire structures. Silicon nanowire arrays with a high aspect ratio of up to 22 can be achieved by tuning several etching parameters [i.e., temperature, oxygen/sulfur hexafluoride (O₂/SF₆) gas mixture ratio, chamber pressure, plasma density, and ion energy]. Higher compressive stress was revealed for longer Si wires by means of Raman spectroscopy. Moreover, an anisotropy of lattice stress was found at the top and sidewall of Si nanowire, indicating compressive and tensile stresses, respectively. From electrochemical characterization, half-cell battery integrating ICP-RIE-based silicon nanowire anode exhibits a capacity of 0.25 mAh cm⁻² with 16.67% capacity fading until 20 cycles, which has to be improved for application in future energy storage devices.

The pursuit of sculpting materials at increasingly smaller and deeper scales remains a persistent subject in the field of micro- and nanofabrication. Anisotropic deep-reactive ion etching of silicon at cryogenic temperatures (cryo-DRIE) was investigated for fabricating arrays of vertically aligned Si nanowires (NWs) of a large range of dimensions from micrometers down to 30 nm in diameter, combined with commonly used wafer-scale lithography techniques based on optical, electron-beam, nanoimprint, and nanosphere/colloidal masking. Large selectivity of ∼100 to 120 and almost 700 was found with resists and chromium hard masks, respectively. This remarkable selectivity enables the successful transfer of patterned geometries while preserving spatial resolution to a significant extent. Depending on the requirements by applications, various shapes, profiles, and aspect ratios were achieved by varying process parameters synchronously or asynchronously. High aspect ratios of up to 100 comparable to the best result by metal-assisted wet-chemical etching and sub-μm trenches by DRIE were obtained with NW diameter of 200 nm, at an etch rate of ∼4 μm/min without being collapsed. At the same time, low surface roughness values were maintained on the NW top, sidewall, and bottom surface of ∼0.3, ∼13, and ∼2 nm, respectively, as well as high pattern fidelity and integrity, which were measured using angle-resolved Fourier microscopy, combined atomic force, and scanning electron microscopy on selected NWs. This work establishes the foundation in the controllable development of Si nanoarchitectures, especially at sub-100 nm structures, for energy-harvesting and storage, damage-free optoelectronics, quantum, photovoltaics, and biomedical devices.

Miniaturization of modern microelectronics to accommodate the development of portable and smart devices requires independent energy storage that is compact, lightweight, reliable, and integrable on-chip. Three-dimensional lithium-ion microbatteries are considered as promising candidates to fill the role, owing to their high energy and power density. Combined with silicon as a high-capacity anode material, the performance of the microbatteries can be further enhanced. In this review, the latest developments in three-dimensional silicon-based lithium-ion microbatteries are discussed in terms of material compatibility, cell designs, fabrication methods, and performance in various applications. We highlight the relation between device architecture and performance as well as comparison between different fabrication technologies. Finally, we suggest possible future studies based on the current development status to provide a research direction towards further improved three-dimensional silicon-based lithium-ion microbatteries.

Due to its high theoretical specific capacity, a silicon anode is one of the candidates for realizing high energy density lithium-ion batteries (LIBs). However, problems related to bulk silicon (e.g., low intrinsic conductivity and massive volume expansion) limit the performance of silicon anodes. In this work, to improve the performance of silicon anodes, a vertically aligned n-type silicon nanowire array (n-SiNW) was fabricated using a well-controlled, top-down nano-machining technique by combining photolithography and inductively coupled plasma reactive ion etching (ICP-RIE) at a cryogenic temperature. The array of nanowires ~1 µm in diameter and with the aspect ratio of ~10 was successfully prepared from commercial n-type silicon wafer. The half-cell LIB with free-standing n-SiNW electrode exhibited an initial Coulombic efficiency of 91.1%, which was higher than the battery with a blank n-silicon wafer electrode (i.e., 67.5%). Upon 100 cycles of stability testing at 0.06 mA cm⁻², the battery with the n-SiNW electrode retained 85.9% of its 0.50 mAh cm⁻² capacity after the pre-lithiation step, whereas its counterpart, the blank n-silicon wafer electrode, only maintained 61.4% of 0.21 mAh cm⁻² capacity. Furthermore, 76.7% capacity retention can be obtained at a current density of 0.2 mA cm⁻², showing the potential of n-SiNW anodes for high current density applications. This work presents an alternative method for facile, high precision, and high throughput patterning on a wafer-scale to obtain a high aspect ratio n-SiNW, and its application in LIBs.

The demand for high-capacity lithium-ion batteries (LIBs) is ever-increasing. Thus, research has been focused on developing silicon-based anodes due to their high theoretical capacity and natural abundance. However, silicon-based anodes still suffer from several drawbacks (e.g., a huge volume expansion during lithiation/delithiation and the low conductivity nature of silicon). In this study, we develop a facile and low-cost synthesis route to create a composite of silicon particles and carbon nanotubes (CNTs) via simple two-step mechanical ball milling with a silicon wafer as the silicon precursor. This method produces a strong interaction between silicon particles and the CNTs, forming Si–C bonds with minimum oxidation of silicon and pulverization of the CNTs. The resulting Si/CNT anode exhibits a first cycle Coulombic efficiency of 98.06%. It retains 71.28% of its first cycle capacity of 2470 mAh g⁻¹ after 100 cycles of charge–discharge at a current density of 400 mA g⁻¹. Furthermore, the Si/CNT anode also shows a good rate capability by retaining 80.15%, and 94.56% of its first cycle capacity at a current density of 1000 mA g⁻¹ and when the current density is reduced back to 200 mA g⁻¹, respectively.

The direct correlation between the surface area of the current collector (CC) and the ‘dead Li’ is evaluated in this study.