A novel scheme is proposed for online condition monitoring of bond wires present in insulated gate bipolar transistor (IGBT) package. The proposed method detects bond wire degradation using on-state collector emitter voltage at the inflection point. Previously reported condition monitoring methods based on on-state collector-emitter voltage as a precursor of aging require an accurate knowledge of junction temperature which is difficult to measure online during an inverter operation. The key advantage of the proposed scheme is that it monitors the bond wire degradation irrespective of the junction temperature. Therefore, this technique is not affected by increase in junction temperature due to die attach degradation or change in ambient temperature. The proposed scheme is verified experimentally under realistic operating conditions.

Reactive power support by photovoltaic (PV) systems is of increasing interest, when compared with the conventional reactive power compensation devices. The PV inverters can exchange reactive power with the utility grid in a decentralized manner even outside feed-in operation, especially at night when there is no solar irradiance. However, reactive power injection causes additional power losses in the switching components leading to a temperature rise in the devices. Thus, this paper analyzes the impact of reactive power injection by PV inverters outside feed-in operation on the thermal performance of their power switching components. A thermal analysis based on the mission profile (i.e., solar irradiance and ambient temperature) has been incorporated, so as to determine the additional temperature rise in the components induced by the operation outside feed-in hours. An analytical lifetime model has been used. The damage produced on the transistors has been quantified using the Palmgren-Miner rule. A reliability analysis has been carried out on a PV inverter with and without the injection of reactive power into the utility grid at night. Economic impacts of injecting reactive power from PV inverters outside feed-in operating hours have been analyzed thereafter. This analysis can be helpful to make a better choice while choosing between conventional reactive power devices or PV inverters for injecting reactive power to the grid.

Medium Voltage (MV) Silicon Carbide (SiC) devices have opened up new areas of applications which were previously dominated by silicon based IGBTs. From the perspective of a power converter design, the development of MV SiC devices eliminates the need for series connected architectures, control of multilevel converter topologies which are necessary for MV applications, and the inherent reliability issues associated with it. However, when SiC devices are used in these applications, they are exposed to a high peak stress (5 kV to 10 kV) and a very high dv/dt (10 kV/ μs to 100 kV/ μs). Using these devices calls for a gate driver with dc-dc isolation stage which has ultra-low coupling capacitance in addition to be able to withstand the high isolation voltage. This paper presents a new MV gate driver design to address these issues while maintaining a minimal footprint for the gate driver. A medium voltage isolation transformer is designed with a low inter-winding capacitance, while maintaining the clearance, creepage, as well as insulation standards. A dc isolation test has been performed to validate the integrity of the insulating material. The key features include low input common mode current, and a short circuit protection scheme specifically designed for 10 kV SiC MOSFETs. The performance of the gate driver is evaluated using double pulse tests and continuous tests. Experimental results validate the advantages of the gate driver and its application for medium voltage SiC devices exhibiting very high dv/dt. The proposed gate driver concept is aimed at providing an efficient and reliable method to drive MV SiC devices.

Owing to low cost, small size and low weight, transformerless inverters became prominent in single-phase grid connected photovoltaic systems. Key issues pertaining to these inverters include suppression of common mode leakage current and improvement of conversion efficiency. Achieving higher efficiency in single-phase grid-connected photo-voltaic systems depends on the number of stages involved in feeding power to the grid, predominantly, if the photovoltaic (PV) array voltage is less than peak value of the grid voltage. In this paper, an integrated dc-dc converter based grid-connected transformerless PV inverter is proposed which is aimed at maintaining a high efficiency even if the PV array voltage falls below the peak value of grid voltage (efficient operation at an extended input voltage range). A modulation strategy is discussed in order to minimize the flow of common-mode leakage current. Further, the efficiencies of certain transformerless inverter topologies are analyzed and compared with that of the proposed topology. Detailed simulation studies are carried out in MATLAB/Simulink environment to verify the analysis. Experimental results for a scaled down laboratory prototype are included as a proof-of-concept to validate the claims.

The emergence of medium-voltage silicon carbide (SiC) power semiconductor devices, in ranges of 10–15 kV, has led to the development of simple two-level converter systems for medium-voltage applications. A medium-voltage mobile utility support equipment-based three-phase solid state transformer (MUSE-SST) system, based on Gen3 10 kV SiC MOSFETs, is developed to interconnect a three-phase 4160 V/60 Hz grid to a three-phase 480 V/60 Hz grid to provide a shore-to-ship power interface for naval vessels. The MUSE-SST system consists of three power conversion stages, namely, MVac/MVdc stage (MV: active front-end converter), MVdc/LVdc stage (dual active bridge converter), and LVdc/LVac stage (LV: active front-end converter). The galvanic isolation is introduced in the MVdc/LVdc stage using MV/LV high-frequency transformers (HFTs). This article demonstrates the operation of the three-phase Y– $\Delta $ connected dual active bridge converter used in the MVdc/LVdc stage of the MUSE-SST system. Equations for phase currents, power flow, and zero-voltage switching (ZVS) boundaries are derived for all possible modes for the three-phase Y– $\Delta $ configuration. A detailed parasitic simulation model is derived by measuring and experimentally verifying the parasitic elements of the HFT. A brief discussion regarding the design considerations required for the hardware development of the medium- and low-voltage sides of the three-phase dual active bridge converter is also provided. Successful tests demonstrating the operation and feasibility of the medium-voltage dual active bridge converter, at medium-voltage levels (7.2 kV dc-link voltage), are shown. The results indicate that these devices can accelerate the growth and deployment of the medium-voltage SiC-based converter for isolated and bidirectional medium- to low-voltage dc systems.

Fast switching characteristic of wide bandgap devices enables high switching frequency of power devices and thereby, can facilitate high fundamental frequency operation of electrical machines. However, with the switching transition times in orders of tens of nanoseconds, the high dv/dt is observed across the switching device. The high dv/dt experienced by the switches, and consequently by the machine, can degrade winding insulations or bearings over a period of time. Therefore, it is imperative to maintain the dv/dt below recommended values depending on the machine insulation. The dv/dt across the devices can be adjusted by varying the gate resistance. A high value of gate resistance, however, introduces additional switching losses on the device. Using different dv/dt filtering techniques can also help to control the dv/dt on the machine terminals. These techniques do not increase the switching losses on the device. However, it introduces additional losses in the filter resistors and also increases the cost of the system. In this paper, an analysis based on the impact of gate resistance on the dv/dt across the machine, and the corresponding losses is carried out. An analytical dv/dt filter design strategy is proposed to limit the dv/dt to a particular value. With the proposed design scheme, the value of each filter component can be easily obtained, and filter losses can be estimated accurately. Lastly, a comparison is performed on the basis of efficiency between these two techniques.