In this article, we first utilize a zero subthreshold swing and zero impact ionization FET (Z2-FET) as an innovative artificial spiking neuron and demonstrate it with CMOS-compatible technology. Owing to the sharp-switching and hysteresis characteristics of Z2-FET, the artificial neuron successfully emulates the key biological neuronal behaviors based on a single device, including threshold-driven spiking and stimulus strength-modulated frequency response. Furthermore, the firing threshold of the neuron is conveniently tuned by the gate voltage, which is helpful in the application of spiking neural networks (SNN). A preliminary endurance up to ${2}\times {10}^{{8}}$ cycles is obtained in the neuron. TCAD simulations further verify the scaling capability of the Z2-FET neuron and its energy consumption is estimated. The results suggest that $\text{Z}^{\vphantom {D^{f}}{2}}$ -FET has great potential for highly compact and energy-efficient artificial spiking neurons.

To mitigate the total ionizing dose (TID) radiation impact, a new structure named double-silicon-on-insulator (DSOI) is introduced in this article. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the device. With this structure, the TID response and TID mitigation strategy using back-bias are discussed in DSOI nMOSFETs. Then, a 3-D TCAD simulation model is proposed to analyze the radiation-induced leakage path for each bias configuration. The impact of negative back-bias during irradiation on trapped charge distribution is given for both buried oxide layer and shallow trench isolation. At last, a 4k-bit static random access memory is used to verify the effectiveness of back-bias on TID-induced leakage current suppression at the circuit level. The experimental results show the possibility of using back-bias against TID threat.

The synergetic effects of total ionization dose and high-temperature stress of silicon on insulator (SOI) FinFETs (FF) are investigated under ON-state bias condition. The experiments and TCAD simulations are employed to analyze the influence of different trapped-charges in the gate and buried oxide on the threshold voltage and mobility variations on the ON-state current of the devices. Results show that the threshold voltage degradation worsens for n-SOI FinFETs but weakens for the p-SOI FinFETs. Also, the ON-state current of n-SOI FinFETs is significantly enhanced, while the change of p-SOI FinFETs is weak under the synergetic effects. The threshold voltage degradation induced by synergetic effects for both n- and p-type SOI FinFETs can exceed the linear superposition of the two types of stresses, which may be related to the thermal release of trapped charges in the gate oxide. The enhanced degradation in the n-SOI FinFETs compared with the p-SOI FinFETs may result from the shallow energy level electron traps in HfO ₂ . Besides, for both n- and p-type SOI FinFETs, the ON-state current variations under the synergetic effects depend on the competitive process of threshold voltage variation and the mobility fluctuation.

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2- $\mu \text{m}$ double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LET _th ) for a DSOI 6T SRAM cell increases by 12.5% with back-gate bias of nMOS reduced from 0 to −15 V.