Driving solutions for power semiconductor devices are experiencing new challenges since the emerging wide bandgap power devices, such as silicon carbide (SiC), with superior performance become commercially available. Generally, high switching speed is desired due to the lower switching loss, yet high dv/dt and di/dt can result in elevated electromagnetic interference (EMI) emission, false-triggering, and other detrimental effects during switching transients. Active gate drivers (AGDs) have been proposed to balance the switching losses and the switching speed of each switching transient. The review of the in-existence AGD methodologies for SiC devices has not been reported yet. This review starts with the essence of the slew rate control and its significance. Then a comprehensive review categorizing the state-of-the-art AGD methodologies is presented. It is followed by a summary of the AGDs control and timing strategies. In this work, using AGD to reduce the EMI noise of a 10 kV SiC MOSFET system is reported. This work also highlights other capabilities of AGDs including reliability enhancement of power devices and rebalancing the mismatched electrical parameters of parallel- and series-connected devices. These application scenarios of AGDs are validated via simulation and experimental results.

Using silicon carbide (SiC) power devices can potentially improve the efficiency of the power electronic system, but it may also introduce severe electromagnetic interference (EMI) problems due to the fast switching speed. The conventional gate driver cannot provide the flexibility to adjust the switching speed of SiC dynamically. To address this issue, an intelligent versatile active gate driver (AGD) is proposed to achieve an optimized switching trajectory for power devices. The proposed AGD has five operation modes, i.e., faster/normal/slower the turn-on process and slower/normal turn-off process. The availability of multiple operation modes offers an extra freedom to improve the switching performance and enable it to be versatile. The proposed AGD can provide more switching speed adjustment resolution than the other AGDs and this feature will allow the proposed AGD to fine tune the switching speed of SiC power devices. In addition, a novel model-based trajectory optimization strategy is proposed to determine the optimal gate driver output voltage by trading the EMI noise against the switching energy losses. The functionalities of the multi-level AGD are validated with the experimental results. The hardware design consideration is also given for the product commercialization purpose.

The silicon carbide (SiC) devices have faster switching speed than that of the conventional silicon (Si) devices, which however may cause excessive device voltage overshoot. Larger gate resistance can help to restrain the overshoot, it however slows down the switching speed and increases switching losses. There are other methods that can mitigate the voltage overshoot, e.g., using low-inductance busbars, adding snubber circuits, etc. In this article, the busbar design for a 250-kW SiC three-level T-type inverter is investigated. The current commutation loops (CCLs) are first analyzed using a single-phase equivalent circuit. Then the detailed busbar design methods, especially a 3-D busbar design concept, are proposed to select the optimal stacking order for the multilayer laminated busbar and to address constraints posed by the physical terminal arrangements of SiC modules and dc-link capacitors. The stray inductance in each CCL is extracted via a finite element analysis and validated on the actual inverter busbar prototypes using an impedance analyzer. To further minimize the busbar stray inductance, a hybrid busbar structure with printed circuit board based buffer circuit using high-frequency decoupling capacitors is designed and evaluated in this article. Finally, the effectiveness of the designed busbars as well as the buffer circuit are validated using experimental studies.

This paper presents a comprehensive design and validation of a compact all silicon carbide (SiC) 250 kW T-type traction inverter with a power density of 25 kW/l and 98.5% peak efficiency. All the operation modes and switching transitions in a T-type phase leg are analyzed to model the semiconductor power losses over a fundamental cycle. Special attention has been paid to investigate the behavior and losses due to the reverse conduction of the SiC MOSFETs. Then a loss model is built based upon this analysis to calculate the device loss distribution and system efficiency, which is further used to determine the optimal switching frequency. In addition, detailed inverter system design and prototyping procedure, including the selection of SiC modules and dc-link capacitors, and the optimization of a 4-layer laminated busbar, are presented. In this work, the T-type phase leg is formed by a normal half bridge module and a common source module. The switching performance and losses in this configuration are different from two-level topology that only uses one SiC module. Therefore, the switching performance and the associated switching energy in each switch position are characterized using a custom clamped inductive load (CIL) test setup designed for a Ttype phase leg. The performance of the full power traction inverter prototype has been verified experimentally using pulse testing and continuous power testing.

Reliability of power systems can be improved by the use of voltage source inverters (VSIs) with fast dynamic control, which can handle uncertainties induced by renewable energy resources and nonlinear loads. To ensure fast-dynamic response and simplified controller design, various model predictive control (MPC) methods are investigated in this paper. In the conventional MPC design for three-level VSIs, the cost function requires an additional term to ensure the balance of the neutral-point voltage (NP-V), which however can considerably impact the main goal of the MPC. To address this issue, an enhanced MPC using virtual space vectors is proposed, which allows the use of a significantly reduced weighting factor for the term in the cost function for NP-V balancing, while retaining fast-dynamic response. Additionally, the proposed MPC leads to reduced harmonic distortion in the VSI output voltage and current. Both simulation and controller hardware-in-the-loop studies are performed to demonstrate the effectiveness of the proposed enhanced MPC in an operating microgrid under both steady-state and fast-transient conditions.

In this paper, a novel finite control set model predictive control (FCS-MPC)-based solution is proposed to eliminate the common-mode voltage (CMV) in matrix converters. Different from the existing MPC-based CMV reduction methods, which usually utilize all the possible switching configurations, in the proposed method, only the six rotating vectors, which produce no CMV, are included in the FCS to synthesize the output voltage and the input current. Therefore, zero CMV can be achieved naturally and no CMV related term needs to be included in the cost function. In addition, compared with other zero CMV methods, e.g., the enhanced space-vector modulation using rotating vectors, the proposed MPC-based method can significantly reduce the computational complexity without detracting the CMV elimination performance. Moreover, a modified four-step commutation strategy is proposed to effectively mitigate the CMV spikes due to the dead time, which usually exists when using the conventional current-based four-step commutation strategy. Finally, the feasibility and effectiveness of the proposed method are validated by using experimental studies.