In this paper, the design of ternary logic gates (standard ternary inverter, ternary NAND, ternary NOR) based on carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) is proposed. Ternary logic has emerged as a very promising alternative to the existing binary logic systems owing to its energy efficiency, operating speed, information density and reduced circuit overheads such as interconnects and chip area. The proposed design employs active load RRAM and CNTFET instead of large resistors to implement ternary logic gates. The proposed ternary logic gates are then utilised to carry out basic arithmetic functions and is extendable to implement additional complex functions. The proposed ternary gates show significant advantages in terms of component count, chip area, power consumption, energy consumption and dense fabrication. The results demonstrate the advantage of the proposed models with a reduction of 50% in transistor count for the STI, TNAND and TNOR logic gates. For THA and THS arithmetic modules 65.11% reduction in transistor count is observed while for TM design, around 38% reduction is observed. In this work, we aim to demonstrate the viability of RRAM in the design of ternary logic systems, thus the focus is mainly on obtaining the proper functionality of the proposed design. Also the proposed logic gates show a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency. For simulations, HSPICE tool is used to verify the authenticity of the proposed designs. The ternary half adder, ternary half subtractor and ternary multiplier circuits are then implemented utilising the proposed gates and validated through simulations.

This letter presents an excellent gain flatness CMOS power amplifier (PA) for UWB applications at 3.0-7.0 GHz in TSMC 0.18 μm CMOS technology. The UWB PA proposed here employs a current-reused technique to enhance the gain at the upper end of the desired band, a shunt and a series peaking inductors with a resistive feedback at the second stage to obtain the wider and flat gain, while shunt-shunt feedback helps to enhance the bandwidth and improve the output wideband matching. The measurement results indicated that the input return loss ( S ₁₁ ) less than -6 dB, output return loss ( S ₂₂ ) less than -7 dB, and excellent gain flatness approximately 14.5 ±0.5 dB over the frequency range of interest. The output 1 dB compression of 7 dBm, the output third-order intercept point (OIP3) of 18 dBm, and a phase linearity property (group delay) of ±178.5 ps across the whole band were obtained with a power consumption of 24 mW.

This letter proposes the design of a low group delay ultra-wideband (UWB) power amplifier (PA) in CMOS technology. The PA design employs a three-stage cascade common source topology that has a different design concept from other multi-stage topology to provide a broad bandwidth characteristic, gain flatness of , and low group delay variation of . A resistive shunt feedback technique is adopted at the first stage of the amplifier to achieve good input matching, which controls the upper frequency of the UWB system. The third stage realizes the gain at the lower corner frequency and the second stage is used to smooth the flatness of the gain curve. By using this method, the proposed design has the lowest group delay variation among the recently reported CMOS PAs for 3.1 to 10.6 GHz applications.

This paper describes the design of 3.1 to 4.8 GHz CMOS power amplifier (PA) for ultra-wideband (UWB) applications using 0.18-μm CMOS technology. The UWB PA proposed here employs cascode topology with a current-reused technique to enhance the gain at the upper end of the desired band, an inter-stage inductor, and a resistive feedback at the second stage to obtain the flatness gain. The measurement results indicated that the input return loss (S11) was less than -5 dB, output return loss (S22) was less than -8 dB, and average power gain of 10.3 dB with a flatness about 0.8 dB. The input 1 dB compression point about -2 dBm and excellent phase linearity (group delay) of ±135 ps across the whole band were obtained. Moreover, a very high power added efficiency (PAE) of 40.5% at 4 GHz with 50 Ω load impedance was achieved with a power consumption of 24-mW.

This paper describes the design of aquaponics water monitoring system using Arduino microcontroller. Arduino Development Environment (IDE) software is used to develop a program for the microcontroller to communicate with multiple sensors and other hardware. The circuit of pH sensor, temperature sensor, water sensor, servo, liquid crystal displays (LCD), peristaltic pump, solar and Global System for Mobile communication (GSM) are constructed and connected to the system. The system powered by a rechargeable battery using solar energy. When the results of pH, temperature and water sensor are out of range, a notification message will be sent to a mobile phone through GSM. If the pH of water is out of range, peristaltic pump is automatic on to maintain back the pH value of water. The water sensor is fixed in the siphon outlet water flow to detect water flow from grow bed to the fish tank. In addition, servo is used to auto feeding the fish for every 12 hours. Meanwhile, the LCD is indicated the pH, temperature, siphon outlet water flow and remaining time for the next feeding cycle. The pH and temperature of water are set in the ranges of 6 to 7 and 25 °C to 30 °C, respectively.

The efficient reduction of graphene oxide (rGO) was performed using Sodium Borohydride (NaBH₄). These reduction approaches remove the majority of the oxygen-containing functional groups at the basal plane and surface of graphene oxide sheets. Structural and physiochemical properties of the GO were investigated with help of Atomic Force Microscopy (AFM), Transmission Electron Microscopy (TEM), Fourier Transform Infrared Spectroscopy (FTIR), and Ultraviolet-Visible-Near infrared (UV-Vis-NIR). The effects of the chemical reduction on a GO surface were analyzed using a Semiconductor Parameter Analyzer (SPA) in order to obtain the electrical resistance measurement. It was found that the resistance of reduced graphene oxide was greatly reduced when compared to the condition of before reduction process. Then, the formation of uniform thin film of rGO sheets was produced using vacuum filtration method in order to fabricate a gas sensor. In this project, plastic was used as a substrate. The sensor was then being exposed to NO₂ gas at room temperature in order to demonstrate the sensing ability of rGO.