In this manuscript, recent progress in the area of resistive random access memory (RRAM) technology which is considered one of the most standout emerging memory technologies owing to its high speed, low cost, enhanced storage density, potential applications in various fields, and excellent scalability is comprehensively reviewed. First, a brief overview of the field of emerging memory technologies is provided. The material properties, resistance switching mechanism, and electrical characteristics of RRAM are discussed. Also, various issues such as endurance, retention, uniformity, and the effect of operating temperature and random telegraph noise (RTN) are elaborated. A discussion on multilevel cell (MLC) storage capability of RRAM, which is attractive for achieving increased storage density and low cost is presented. Different operation schemes to achieve reliable MLC operation along with their physical mechanisms have been provided. In addition, an elaborate description of switching methodologies and current voltage relationships for various popular RRAM models is covered in this work. The prospective applications of RRAM to various fields such as security, neuromorphic computing, and non-volatile logic systems are addressed briefly. The present review article concludes with the discussion on the challenges and future prospects of the RRAM.

In this paper, the design of ternary logic gates (standard ternary inverter, ternary NAND, ternary NOR) based on carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM) is proposed. Ternary logic has emerged as a very promising alternative to the existing binary logic systems owing to its energy efficiency, operating speed, information density and reduced circuit overheads such as interconnects and chip area. The proposed design employs active load RRAM and CNTFET instead of large resistors to implement ternary logic gates. The proposed ternary logic gates are then utilised to carry out basic arithmetic functions and is extendable to implement additional complex functions. The proposed ternary gates show significant advantages in terms of component count, chip area, power consumption, energy consumption and dense fabrication. The results demonstrate the advantage of the proposed models with a reduction of 50% in transistor count for the STI, TNAND and TNOR logic gates. For THA and THS arithmetic modules 65.11% reduction in transistor count is observed while for TM design, around 38% reduction is observed. In this work, we aim to demonstrate the viability of RRAM in the design of ternary logic systems, thus the focus is mainly on obtaining the proper functionality of the proposed design. Also the proposed logic gates show a very small variation in power consumption and energy consumption with variation in process parameters, temperature, output load, supply voltage and operating frequency. For simulations, HSPICE tool is used to verify the authenticity of the proposed designs. The ternary half adder, ternary half subtractor and ternary multiplier circuits are then implemented utilising the proposed gates and validated through simulations.

The capability of multiple valued logic (MVL) circuits to achieve higher storage density when compared to that of existing binary circuits is highly impressive. Recently, MVL circuits have attracted significant attention for the design of digital systems. Carbon nanotube field effect transistors (CNTFETs) have shown great promise for design of MVL based circuits, due to the fact that the scalable threshold voltage of CNTFETs can be utilized easily for the multiple voltage designs. In addition, resistive random access memory (RRAM) is also a feasible option for the design of MVL circuits, owing to its multilevel cell capability that enables the storage of multiple resistance states within a single cell. In this manuscript, a design approach for ternary combinational logic circuits while using CNTFETs and RRAM is presented. The designs of ternary half adder, ternary half subtractor, ternary full adder, and ternary full subtractor are evaluated while using Synopsis HSPICE simulation software with standard 32 nm CNTFET technology under different operating conditions, including different supply voltages, output load variation, and different operating temperatures. Finally, the proposed designs are compared with the state-of-the-art ternary designs. Based on the obtained simulation results, the proposed designs show a significant reduction in the transistor count, decreased cell area, and lower power consumption. In addition, due to the participation of RRAM, the proposed designs have advantages in terms of non-volatility.

Numerous works that have demonstrated the study and enhancement of switching properties of ZnO-based RRAM devices are discussed. Several native point defects that have a direct or indirect effect on ZnO are discussed. The use of doping elements, multi-layered structures, suitable bottom and top electrodes, controlling the deposition materials, and the impact of hybrid structure for enhancing the switching dynamics are discussed. The potentials of ZnO-based RRAM for invisible and bendable devices are also covered. ZnO-based RRAM has the potential for possible application in bio-inspired cognitive computational systems. Thus, the synapse capability of ZnO is presented. The sneak-path current issue also besets ZnO-based RRAM crossbar array architecture. Hence, various attempts to subdue the bottleneck have been shown and discussed in this article. Interestingly, ZnO provides not only helpful memory features. However, it demonstrates the ability to be used in nonvolatile multifunctional memory devices. Also, this review covers various issues like the effect of electrodes, interfacial layers, proper switching layers, appropriate fabrication techniques, and proper annealing settings. These may offer a valuable understanding of the study and development of ZnO-based RRAM and should be an avenue for overcoming RRAM challenges.

The rapid advancement of new technologies has resulted in a surge of data, while conventional computers are nearing their computational limits.

The research interest in the field of carbon nanotube field effect transistors (CNTFETs) in the post Moore era has witnessed a rapid growth primarily due to the fact that the conventional silicon based complementary metal oxide semiconductor (CMOS) devices are approaching its fundamental scaling limits. This has led to significant interest among the researchers to examine novel device technologies utilizing different materials to sustain the scaling limits of the modern day integrated circuits. Among various material alternatives, carbon nanotubes (CNTs) have been extensively investigated owing to their desirable properties such as minimal short channel effects, high mobility, and high normalized drive currents. CNTs form the most important component of CNTFETs, which are being viewed as the most feasible alternatives for the replacement of silicon transistors. In this manuscript, detailed description of the recent advances of state of the art in the field of CNTFETs with emphasis on the most broadly impactful applications for which they are being employed is presented. The future prospects of CNTFETs while considering aggressively scaled transistor technologies are also briefly discussed.