In this article, a low-cost quadruple-node-upsets resilient latch (LCQRL) design is proposed. To meet the high-reliability demands of safety-critical applications, the latch integrates nine soft-error-interceptive modules (SIMs) to form robust feedback loops, ensuring complete resilience to quadruple-node upsets (QNUs). Each Sim comprises ten CMOS transistors and a clocked inverter. Notably, C-element (CE) and dual interlocked storage cell (DICE) modules are not employed in this circuit, resulting in a small area and low power consumption. The simulation results verify the complete QNU self-recoverability and cost-effectiveness of this design. Compared with the existing radiation-hardened QNU resilient latches, the LCQRL latch demonstrates significant improvements in area, power consumption, and area–power–delay product (APDP) by 47.8%, 63%, and 75.5%, respectively. Furthermore, it exhibits low sensitivity to process, voltage, and temperature (PVT) variations.

In this article, a power-on-reset (POR) circuit with accurate trigger-point voltage and ultralow typical quiescent current for emerging nonvolatile memory (NVM) is presented. To keep the trigger-point voltage from the effect of process, voltage, and temperature (PVT) and supply ramp rate variations, low-cost current generators and a current comparator are adopted with brown-out detection (BOD). A protection circuit is utilized for correct operations in different BOD events. Meanwhile, delay blocks are utilized to generate reliable pulse signals that are less influenced by temperature and supply ramp rate. The simulation results show that the trigger-point voltage is 2.08 V with a temperature coefficient (TC) of 81.8 ppm/ $^{\circ}$ C and a deviation to the ramp time of 9.91% for a wide ramp time range from 10 $\mu $ s to dc. In addition, the reset duration time of the POR pulse is also reliable. The proposed POR circuit designed in the 55-nm CMOS process consumes only 0.65-nA typical quiescent current and 59 $\times$ 146 $\mu $ m area, which is suitable for emerging NVM systems.

In this paper, a fast-transient-response NMOS low-dropout regulator (LDO) with a wide load-capacitance range was presented to provide a V/2 read bias for cross-point memory. To utilize the large dropout voltage in the V/2 bias scheme, a fast loop consisting of NMOS and flipped voltage amplifier (FVA) topology was adopted with a fast transient response. This design is suitable to provide a V/2 read bias with 3.3 V input voltage and 1.65 V output voltage for different cross-point memories. The FVA-based LDO designed in the 110 nm CMOS process remained stable under a wide range of load capacitances from 0 to 10 nF and equivalent series resistance (ESR) conditions. At the capacitor-less condition, it exhibited a unity-gain bandwidth (UGB) of approximately 400 MHz at full load. For load current changes from 0 to 10 mA within an edge time of 10 ps, the simulated undershoot and settling time were only 144 mV and 50 ns, respectively. The regulator consumed 70 µA quiescent current and achieved a remarkable figure-of-merit (FOM) of 1.01 mV. At the ESR condition of a 1 µF off-chip capacitor, the simulated quiescent current, on-chip capacitor consumption, and current efficiency at full load were 8.5 µA, 2 pF, and 99.992%, respectively. The undershoot voltage was 20 mV with 800 ns settling time for a load step from 0 to 100 mA within the 10 ps edge time.