In this article, a low-cost quadruple-node-upsets resilient latch (LCQRL) design is proposed. To meet the high-reliability demands of safety-critical applications, the latch integrates nine soft-error-interceptive modules (SIMs) to form robust feedback loops, ensuring complete resilience to quadruple-node upsets (QNUs). Each Sim comprises ten CMOS transistors and a clocked inverter. Notably, C-element (CE) and dual interlocked storage cell (DICE) modules are not employed in this circuit, resulting in a small area and low power consumption. The simulation results verify the complete QNU self-recoverability and cost-effectiveness of this design. Compared with the existing radiation-hardened QNU resilient latches, the LCQRL latch demonstrates significant improvements in area, power consumption, and area–power–delay product (APDP) by 47.8%, 63%, and 75.5%, respectively. Furthermore, it exhibits low sensitivity to process, voltage, and temperature (PVT) variations.

Multilevel cell (MLC) phase change memory (PCM) not only helps in reducing the cost-per-bit of novel nonvolatile memory but also proves to be well-suited for neuromorphic computing, due to its continuously adjustable conductance. However, conventional MLC PCM devices suffer from significant bottlenecks associated with process variability, device loss, energy efficiency, and speed, which hinder their further development. This article proposes a hybrid programming algorithm for MLC PCM devices that employs one-shot preprogram and graded iterations to speed up the convergence of intermediate conductance while consuming lower power and experiencing less device loss. Test experiments conducted on a 64M-cell PCM chip, operating at 4 bits/cell, demonstrate that the proposed scheme is effective in reducing program time and power consumption by 82.3% and 82.6%, respectively, compared to traditional program schemes. Furthermore, the classification of handwritten MNIST datasets using PCM synapses yielded an accuracy of 94.22%, which was further improved to 97.32% by limiting the weight range through software optimization.

In this article, a power-on-reset (POR) circuit with accurate trigger-point voltage and ultralow typical quiescent current for emerging nonvolatile memory (NVM) is presented. To keep the trigger-point voltage from the effect of process, voltage, and temperature (PVT) and supply ramp rate variations, low-cost current generators and a current comparator are adopted with brown-out detection (BOD). A protection circuit is utilized for correct operations in different BOD events. Meanwhile, delay blocks are utilized to generate reliable pulse signals that are less influenced by temperature and supply ramp rate. The simulation results show that the trigger-point voltage is 2.08 V with a temperature coefficient (TC) of 81.8 ppm/ $^{\circ}$ C and a deviation to the ramp time of 9.91% for a wide ramp time range from 10 $\mu $ s to dc. In addition, the reset duration time of the POR pulse is also reliable. The proposed POR circuit designed in the 55-nm CMOS process consumes only 0.65-nA typical quiescent current and 59 $\times$ 146 $\mu $ m area, which is suitable for emerging NVM systems.

Phase change memory (PCM) is considered one of the most promising candidates for next-generation non-volatile memory, owing to its scalability, durability, and cost-effectiveness. However, with the shrinking of device sizes and the reduction in supply voltages, achieving high-speed and reliable readouts in PCM has become increasingly challenging due to process variations. To address this, the dual-sensing-margin offset-compensated sense amplifier (DSOC-SA) is proposed. The DSOC-SA achieves the highest sensing margin, and the lowest read energy consumption compared to traditional sense amplifiers by utilizing a dual-sensing-margin structure, offset compensation, and strong positive feedback. Simulation results demonstrate that, compared to differential sense amplifier and offset-canceling current-sampling sense amplifier, DSOC-SA achieves a 5.6× and 1.6× improvement in sensing speed, respectively, while reducing power consumption by 87.1% and 51.2%.