Multilevel inverters (MLIs) with switched-capacitor (SC) units have been a widely rehearsed research topic in power electronics since the last decade. Inductorless/transformerless operation with voltage-boosting feature and inherent capacitor self-voltage balancing performance with a reduced electromagnetic interference make the SC-MLI an attractive converter over the other available counterparts for various applications. There have been many developed SC-MLI structures recently put forward, where different basic switching techniques are used to generate multiple (discrete) output voltage levels. In general, the priority of the topological development is motivated by the number of output voltage levels, overall voltage gain, and full dc-link voltage utilization, while reducing the component counts and stress on devices for better efficiency and power density. To facilitate the direction of future research in SC-MLIs, this article presents a comprehensive review, critical analysis, and categorization of the existing topologies. Common fundamental units are generalized and summarized with their merits and demerits. Ultimately, major challenges and research directions are outlined leading to the future technology roadmap for more practical applications.

A two-stage switched-capacitor based multilevel inverter possesses a drawback such that switches in the second stage (i.e. H-bridge) endure higher voltage stress. To resolve this problem, this letter proposes a single-stage switched-capacitor module (S3CM) topology for cascaded multilevel inverter which ensures the peak inverse voltage across all switches within the dc source voltage. Nine voltage levels can be generated with only one dc source and two incorporated capacitors. Hence, the number of isolated dc sources are significantly reduced compared to cascaded H-bridge. In addition, voltage boosting gain of two is achieved. A comparative analysis against the recent topology reveals that the proposed S3CM topology achieves switch count reduction. The operation of the proposed topology is validated through circuit analysis followed by experimental results of a single module (9-level) prototype.

The conventional three-level active-neutral-point-clamped (ANPC) inverter requires high dc-link voltage at least twice the peak of ac output. To reduce the dc-link voltage, a recent topology that enhanced the voltage gain from half to unity has been presented. In this letter, an alternative ANPC topology is established by using two T-type inverters. Two floating capacitors with self-voltage balancing capability are integrated to achieve a voltage-boosting gain of 1.5. In addition, the proposed topology is capable of generating seven voltage levels. Its operation is validated through circuit analysis followed by experimental results of a prototype.

This paper proposes a new family of multilevel inverter topology that is able to generate seven voltage levels by utilizing one or two floating capacitors and ten power switches. This novel boost switched-capacitor 7-level inverter (BSC7LI) possesses voltage boosting capability with an achievable maximum voltage level 1.5 times the input direct current (dc) voltage. The generation of higher output voltage does not incur high-voltage stress on any power switch in this topology, as the peak inverse voltages of all power switches do not exceed the input source voltage. In addition, capacitor voltage balancing is not essential since the floating capacitors are effectively balanced during the charging and discharging processes. Furthermore, the proposed topology eliminates the need for multiple isolated dc sources, and a single dc source is sufficient in both its single-phase and three-phase topologies. The operating principle and steady-state analysis of the proposed topology are elaborated. Experimental results from a single-phase prototype are then presented to verify the validity of the proposed topology.

Recent research on common-ground switched-capacitor transformerless (CGSC-TL) inverters shows some intriguing features, such as integrated voltage boosting ability, possible multilevel output voltage generation, and nullification of the leakage current issue. However, the number of output voltage levels and also the overall voltage boosting ratio of most of the existing CGSC-TL inverters are limited to five and two, respectively. This article presents a generalized circuit configuration of such converters capable of higher voltage gain and output voltage levels generation. A basic five-level (5L) CGSC-TL inverter is first proposed using eight power switches and two self-balanced dc-link capacitors. A generalized extension of the circuit for any output voltage levels and voltage gain is then presented while keeping all the traits of the proposed basic 5L-CGSC-TL inverter. The circuit descriptions, control strategy, design guidelines, comparative study, and the relevant simulation and experimental results for the proposed 5L-CGSC-TL inverters and its seven-level derived topology are presented to validate the effectiveness and feasibility of this proposal.

Conventional active-neutral-point-clamped (ANPC) inverters exhibit low voltage gain that inherently leads to a high dc-link voltage requirement. An improved ANPC inverter that is capable of generating five voltage levels has recently reduced the dc-link voltage twofold to achieve unity gain. This led to the development of a single-stage dc-ac power converter with no frontend boost dc-dc converter. This paper proposes novel ANPC inverters capable of unity or boosted voltage gain while generating higher voltage levels. The first topology can provide a voltage gain of 1.5 and extends the number of levels to seven by incorporating only one additional switch. The topology can also be extended by adding three switches and one floating capacitor to generate nine levels with unity voltage gain, or eleven levels with a voltage gain of 2.5. The proposed ANPC inverters and their operations are comprehensively discussed. Experimental results are provided to validate the feasibility of the proposed ANPC inverters.