New voltage-mode min/max circuits are introduced that have a simple architecture. Unlike conventional winner-take-all or source follower based schemes, the proposed circuits are characterised by reduced voltage swing at all internal nodes and by a very low output impedance, which enables them to provide high-speed and high-precision operation. Their complexity grows linearly with the number of inputs. The characterisation of a test chip prototype has provided experimental verification of these features.

Wide band-gap (WBG) semiconductors technology represents a potential candidate to displace conventional silicon (Si) technology used in power electronics. Between Silicon Carbide (SiC) and Gallium Nitride (GaN) power semiconductors, the latter is the least mature of both technologies, with many open research problems, especially in the aerospace industry. In this paper, we address the design and implementation of a DC/DC converter for a hybrid small unmanned aerial vehicle (UAV) based on GaN technology. Both theoretical and simulation comparisons of Si, SiC and GaN transistors for the converter are presented. The conclusion is that GaN devices are the most appropriate to fulfill converter requirements for the size and weight limitations of the selected UAV. The paper presents a buck converter which handles an input voltage range of 32 V to 40 V and provides a 12 V regulated output and output power up to 60 W. The experimental results carried out on the prototype converter show how promising the GaN technology is for aerospace systems, not only regarding its volume and size, but also its efficiency. Besides, practical implementation details are reported to contribute to the design of small, light and reliable GaN power converters for aeronautics.

Sigma-delta modulator based DACs are simple circuits with low accuracy requirements in their analog components. However, their signal bandwidth is limited by speed constrains. Time-Interleaving allows the designer to trade-off between complexity and speed by replacing the original architecture by a number M of parallel paths clocked at a frequency M times smaller. The M digital outputs of the low-rate parallel paths are time multiplexed in a unique path at the high rate and converted to analog by means of a DAC. Unfortunately, this DAC must be also clocked at the high rate, it imposes severe restrictions on performances, and can limit the maximum frequency of operation. In this paper, the time multiplexing is performed in the analog domain by means of M DACs clocked at the low rate. The resulting architecture is more robust against dynamic effects. The main limitation introduced by the proposed architecture comes from mismatch in the DACs’ gain, which can drastically impact performances. A new technique of dynamic elements matching is proposed here to overcome this problem. The proposed architecture benefits from the advantages of the return-to-zero pulses but, unlike a conventional DAC, maintains the robustness against clock jitter.

A linear tunable CMOS transconductor is proposed which uses a new low-voltage supercascode transistor to provide a high output resistance. Using a standard 0.8 µm CMOS technology, simulation results are provided that show the operation of the proposed transconductor with a 1.2 V peak-to-peak differential input signal and 1.5 V supply voltage. The proposed transconductor features a high linearity and more than 100 MHz bandwidth.