A high-precision current-mode bandgap reference (BGR) circuit with a high-order temperature compensation is presented in this paper. In order to achieve a high-precision BGR circuit, the equation of the nonlinear current has been modified and the high-order term of the current flowing into the nonlinear compensation bipolar junction transistor (NLCBJT) is compensated further. According to the modified equation, two solutions are designed to improve the output accuracy of BGR circuits. The first solution is to divide the NLCBJT branch into two branches to reduce the coefficient of the nonlinear temperature compensation current. The second solution is to inject the nonlinear current into the two branches based on the first one to further eliminate the temperature coefficient (TC) of the current flowing into the NLCBJT. The proposed BGR circuit has been designed using the Semiconductor Manufacturing International Corporation (SMIC) 55 nm CMOS process. The simulation results show that the variations in currents flowing into NLCBJTs improved from 148.41 nA to 69.35 nA and 7.4 nA, respectively, the TC of the output reference current of the proposed circuit is approximately 3.78 ppm/°C at a temperature range of −50 °C to 120 °C with a supply voltage of 3.3 V, the quiescent current consumption of the entire BGR circuit is 42.13 μA, and the size of the BGR layout is 0.044 mm², leading to the development of a high-precision BGR circuit.

A fully integrated low-dropout (LDO) regulator with improved load regulation and transient responses in 40 nm technology is presented in this paper. Combining adjustable threshold push–pull stage (ATPS) and master–slave power transistors topology, the proposed LDO maintains a three-stage structure within the full load range. The proposed structure ensures the steady-state performance of LDO and achieves 0.017 mV/mA load regulation. The ATPS consumes little quiescent current at light load current condition, and the turn-on threshold of the ATPS can be adjusted by a current source. Once the value of current source is set, the turn-on threshold is also determined. A benefit of the proposed structure is that the LDO can be stable from 0 to 100 mA load current with a maximum 100 pF parasitic load capacitance and a 0.7 pF compensation capacitor. It also shows good figure of merit (FOM) without an extra transient enhanced circuit. For the maximum 100 mA load transient with 100 ns edge time, the undershoot and overshoot are less than 33 mV. The dropout voltage of the regulator is 200 mV with input voltage of 1.1 V. The total current consumption of the LDO was 24.6 μA at no load.

A novel output-capacitorless low-dropout regulator (OCL-LDO) with an embedded slew-rate-enhancement (SRE) circuit is presented in this paper. The SRE circuit adopts a transient current-boost strategy to improve the slew rate at the gate of the power transistor when a large voltage spike at the output is detected. In addition, a feed-forward transconductance cell is introduced to form a push–pull output structure with the power transistor. The simulation results show that the maximum transient output voltage variation is $23.5 \mathrm{mV}$ when the load current $I_{LOAD}$ is stepped from $0$ to $100 \mathrm{mA}$ in $100 \mathrm{ns}$ with a load capacitance of $100 \mathrm{pF}$, and the settling time is $1.2 \mathsf{\mu }\mathrm{s}$. The proposed OCL-LDO consumes a quiescent current of $30 \mathsf{\mu }\mathrm{A}$ and has a dropout voltage of $200 \mathrm{mV}$ for the maximum output current of $100 \mathrm{mA}$.