A flux-controlled memristor emulator built with off-the-shelf electronic devices and based on a TiO₂ model is presented in this article. The circuit proposed in this article uses the current mode approach based analog building blocks such as a second-generation current conveyor (CCII) and an operational transconductance amplifier (OTA) as an active element with few passive elements. The circuit shows a clear fingerprint of an ideal memristor. The offered emulator circuit can be made to operate in incremental and decremental modes and functions well up to 26.3 MHz. Nonvolatility, Monte Carlo sampling, and corner analysis simulations are executed to verify the robustness of the circuit. The functional verification of the presented circuit is performed using the 0.18-μm CMOS parameter at a supply voltage of ±1.2 V. The experimental demonstration is carried out by making a prototype on a breadboard using ICs AD844AN and CA3080, which exhibits a good agreement with theoretical and simulation results. The layout of the circuit, which requires a total chip area of 75 x 70 μm², is also created. Single/parallel combinations of a memristor, a high-pass filter, and a chaotic system are presented to demonstrate its application.

In this article, a new solution for an ultralow-voltage (ULV) ultralow-power (ULP) operational transconductance amplifier (OTA) is presented. Thanks to the combination of a low-voltage bulk-driven nontailed differential stage with the multipath Miller zero compensation technique, a simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time. The proposed OTA was fabricated using the 180-nm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC) and can operate from VDD ranging from 0.3 to 0.5 V. The 0.3-V version dissipates only 12.6 nW of power while showing a 64.7-dB voltage gain at 1-Hz, 2.96-kHz gain-bandwidth product, and a 4.15-V/ms average slew-rate at 30-pF load capacitance. The measured results agree well with simulations.

A new solution for an ultra-low-voltage, ultra-low-power operational transconductance amplifier (OTA) is presented in the paper. The design exploits a three-stage structure with a Reversed Miller Compensation Scheme, where the input stage is based on a non-tailed bulk-driven differential pair. Optimization of the structure for very low supply voltage is discussed. The resulting amplifier outperforms other ultra-low-voltage OTAs in terms of a DC voltage gain and power efficiency, expressed by standard figures of merit. Experimental verification using a 0.18μm CMOS technology, with supply voltage of 0.3-V, showed a dissipation power of 13 nW, a DC voltage gain of 98 dB, a gain-bandwidth product of 3.1 kHz and an average slew-rate of 9.1 V/ms at 30 pF load capacitance. The experimental results agree well with simulations.