Dr. Tomasz Kulej

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Academic Career Length

35Years (1992-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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13 September 2019 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Journal Article

A Compact 0.3-V Class AB Bulk-Driven OTA

Tomasz Kulej

Fabian Khateb

In this article, a new solution for an ultralow-voltage (ULV) ultralow-power (ULP) operational transconductance amplifier (OTA) is presented. Thanks to the combination of a low-voltage bulk-driven nontailed differential stage with the multipath Miller zero compensation technique, a simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time. The proposed OTA was fabricated using the 180-nm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC) and can operate from VDD ranging from 0.3 to 0.5 V. The 0.3-V version dissipates only 12.6 nW of power while showing a 64.7-dB voltage gain at 1-Hz, 2.96-kHz gain-bandwidth product, and a 4.15-V/ms average slew-rate at 30-pF load capacitance. The measured results agree well with simulations.

25 March 2018 in International Journal of Circuit Theory and Applications

Journal Article

Design and implementation of sub 0.5‐V OTAs in 0.18‐μm CMOS

Tomasz Kulej

Fabian Khateb

6 February 2020 in IEEE Access

Journal Article

A 0.3-V 98-dB Rail-to-Rail OTA in $0.18~\mu$ m CMOS

Tomasz Kulej

Fabian Khateb

A new solution for an ultra-low-voltage, ultra-low-power operational transconductance amplifier (OTA) is presented in the paper. The design exploits a three-stage structure with a Reversed Miller Compensation Scheme, where the input stage is based on a non-tailed bulk-driven differential pair. Optimization of the structure for very low supply voltage is discussed. The resulting amplifier outperforms other ultra-low-voltage OTAs in terms of a DC voltage gain and power efficiency, expressed by standard figures of merit. Experimental verification using a 0.18μm CMOS technology, with supply voltage of 0.3-V, showed a dissipation power of 13 nW, a DC voltage gain of 98 dB, a gain-bandwidth product of 3.1 kHz and an average slew-rate of 9.1 V/ms at 30 pF load capacitance. The experimental results agree well with simulations.

1 November 2013 in IET Circuits, Devices & Systems

Journal Article

0.5‐V bulk‐driven CMOS operational amplifier

Tomasz Kulej

A new solution for a low‐voltage bulk‐driven CMOS operational amplifier is presented in this study. The amplifier is designed using 50 nm process parameters and optimised for 0.5 V supply voltage. The circuit consumes 100 μW, performing 74 dB open‐loop gain, 59 nV/Hz ^1/2 input referred noise at 1 MHz and 4.8 MHz gain bandwidth product (GBP) for 20 pF load capacitance.

19 September 2022 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Journal Article

A 0.5-V Multiple-Input Bulk-Driven OTA in 0.18-μm CMOS

This article presents the experimental results for a multiple-input operational transconductance amplifier (MI-OTA). To achieve extended linearity under 0.5-V low voltage supply, the circuit employs three linearization techniques: the bulk-driven (BD), the source degeneration, and the input voltage attenuation created by the MI metal-oxide-semiconductor transistor technique (MI-MOST). Although the linearization techniques result in reduced dc gain, the self-cascode transistors are used to boost the gain of the MI-OTA. Furthermore, the MI-MOST simplifies the internal structure of the OTA and may reduce the complexity of the applications. The MI-OTA operates in the subthreshold region and offers tunability by a bias current in the nanoampere range. The circuit is capable to work with 0.5-V supply voltage while consuming 24.77 nW. The circuit was fabricated using the 0.18- $\mu \text{m}$ Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology and it occupies a 0.01153-mm2 silicon area. Intensive simulation and experimental results confirm the benefits and robustness of the design.

6 September 2018 in IEEE Transactions on Circuits and Systems I: Regular Papers

Journal Article

Design and Implementation of a 0.3-V Differential Difference Amplifier

Fabian Khateb

Tomasz Kulej

A new silicon realization of an ultra-low-voltage and ultra-low-power differential-difference amplifier (DDA) is presented in this paper. The circuit combines the idea of non-tailed bulk-driven differential pairs with a partial positive feedback used for voltage gain boosting. The DDA operates from VDD ranging from 0.3 to 0.5 V. For a 0.3-V version, the circuit provides measured DC voltage gain larger than 60 dB, the GBW product of 1.85 kHz, PSRR of 57 dB and the average slew-rate of 1.55 V/ms at 20 pF load capacitance, while consuming only 22 nW of power. An instrumentation amplifier based on the proposed DDA showed the THD of 0.5 % for Vin = 50 mVpp, and the 3-dB bandwidth of 750 Hz with the voltage gain of 2 V/V. The circuit has been fabricated in a standard n-well 0.18 μm CMOS process from TSMC. Chip test results agree with simulations. A special design procedure has also been developed that allows the circuit to be optimized under such extreme supply conditions.

About Me

Dr. Tomasz Kulej received the M.Sc. and Ph.D. degrees from the Gdańsk University of Technology, Gdańsk, Poland, in 1990 and 1996, respectively. He was a Senior Design Analysis Engineer with the Polish Branch, of Chipworks Inc., Ottawa, Canada. He is currently an Associate Professor with the Department of Electrical Engineering, Czestochowa University of Technology, Poland, where he conducts lectures on electronics fundamentals, analog circuits, and computer-aided design. He has authored or co-authored more than 90 publications in peer-reviewed journals and conferences. He holds three patents. His current research interests include analog integrated circuits in CMOS technology, with an emphasis on low-voltage and low-power solutions. He serves as an Associate Editor for the Circuits, Systems, and Signal Processing and IET Circuits Devices and Systems. He was a Guest Editor for the Special Issue on Low-Voltage Integrated Circuits of the Circuits Systems and Signal Processing, in 2017, IET Circuits Devices and Systems, in 2018, and Microelectronics Journal, in 2019.

Dr. Tomasz Kulej

Dr. Tomasz Kulej

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