A flux-controlled memristor emulator built with off-the-shelf electronic devices and based on a TiO₂ model is presented in this article. The circuit proposed in this article uses the current mode approach based analog building blocks such as a second-generation current conveyor (CCII) and an operational transconductance amplifier (OTA) as an active element with few passive elements. The circuit shows a clear fingerprint of an ideal memristor. The offered emulator circuit can be made to operate in incremental and decremental modes and functions well up to 26.3 MHz. Nonvolatility, Monte Carlo sampling, and corner analysis simulations are executed to verify the robustness of the circuit. The functional verification of the presented circuit is performed using the 0.18-μm CMOS parameter at a supply voltage of ±1.2 V. The experimental demonstration is carried out by making a prototype on a breadboard using ICs AD844AN and CA3080, which exhibits a good agreement with theoretical and simulation results. The layout of the circuit, which requires a total chip area of 75 x 70 μm², is also created. Single/parallel combinations of a memristor, a high-pass filter, and a chaotic system are presented to demonstrate its application.

This paper proposes a charged controlled emulator model for memristor and memcapacitor using second-generation Current Conveyor (CCIIs) and Analog Multiplier (AM). The grounded and floating mem-element circuits have been designed using two CCIIs and one multiplier in addition to some passive components. The grounded type of design requires three resistors and three capacitors while floating design necessitates only two resistors and two capacitors. With the help of a switch, the proposed design can be easily switched into a memristor or memcapacitor. The proposed emulator model has been theoretically analyzed and simulated in PSpice to substantiate the effectiveness and accuracy. The practicability of the circuit has been established using commercially available ICs AD844AN and AD633JN. Non-linear characteristics of the proposed memristor emulator have been used to design a chaotic system.

In this study, a high‐frequency floating‐type memristor emulator has been presented. The proposed emulator circuit uses a current conveyor transconductance amplifier, second generation current conveyor, three resistors and a grounded capacitor. The presented floating‐type memristor can be configured in both incremental and decremental configurations and performs well up to 5 MHz. The equivalent memristor equation is verified by theoretical analysis of the proposed circuit which also includes non‐ideal analysis. The theoretical proposition has been verified through personal simulation program with integrated circuit emphasis simulations using TSMC 0.25 μm complementary metal oxide semiconductor technology parameters. Moreover, non‐volatility and Monte Carlo simulation have been performed to check the robustness of the circuit. The effectiveness of the presented memristor emulator design has been verified by printed circuit board prototype using commonly available integrated circuits AD844 and CA3080. The experimental results are included, which show good agreement with the theoretical and simulation results. To test the functionalities of the proposed designs, their applications as parallel and serial combinations, high‐pass filter and Chua's oscillator have been presented.

This article presents a novel charge-controlled memristor emulator circuit. The proposed memristor emulator utilizes a single Current Follower Transconductance Amplifier (CFTA) as an active current mode analog building block and a grounded capacitor as a passive element. The circuit presented follows all the fingerprints of an ideal memristor. It operates in both incremental as well as decremental mode. The functional performance of the emulator circuit is verified at different operating frequencies and performs well up to 9 MHz. The theoretical and non-ideal analyses are verified for the proposed emulator. Moreover, Monte Carlo sampling and non-volatility analysis are performed to investigate the robustness of the emulator circuit. The functionality of the proposed model has been verified through PSPICE simulation using TSMC 0.18 μm CMOS technology at the supply voltage of ±1.2 V. The experimental confirmation of the presented circuit is also performed by building a breadboard micromodel using ICs CA3080 and AD844AN. Memristor based Chua's circuit model is included as one of its applications.