Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future.

We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

This paper presents characterization and modeling results exploring the temperature dependence of the electrical characteristics of 3-D NAND Flash strings. Experimental data over a wide temperature range are used to calibrate a Technology Computer-Aided Design model for current transport through the polysilicon channel of the strings, which is then used to investigate the role of grain boundaries on string conduction. Results reveal that the variability in the grain configuration in the strings introduces a nonnegligible statistical spread in the temperature dependence of the threshold voltage (VT) of the memory cells, which acts as a broadening contribution to the array VT distribution when temperature is changed. The experimental and modeling activities will be extended in Part II of this paper to explore the temperature dependence of the VT instability caused by random telegraph noise.

This letter investigates the major differences between planar (2-Dimensional, 2-D) and vertical-channel (3- Dimensional, 3-D) NAND Flash memory arrays in terms of their temperature dependences. Attention is focused on three relevant parameters for memory array operation, namely, cell thresholdvoltage, string saturation current and width of the random telegraph noise distribution. Results highlight that the transition from 2-D to 3-D arrays introduced non-negligible changes in the temperature behavior of these parameters, whose origin is traced back to the different channel material of the technologies, i.e. monocrystalline vs. polycrystalline silicon.