The aim of this study is to identify practices that would enable building construction companies to adopt agile project management methodologies during the design stage of projects that use building information modelling (BIM) solutions in the designing process. Due to the benefits of agile project management methodologies, a considerable amount of research has been conducted regarding the adoption of this methodology for building construction projects. However, waterfall project management is still more widely used in the building construction industry than agile project management is. Several recent studies claim that firms could focus on adopting agile methodologies during the design stage of a building construction project because due to the advent of BIM software solutions, the design stage can be carried out in a manner such as a software development project. Since software development industry is experiencing a widespread adoption of agile methods, if the design stage of a building construction project can be carried out such as a software development project, then there is a possibility to drive agile adoption in the design stage. Based on this information, researchers found an architectural consultancy firm that has been using a BIM solution to adopt agile project management methodologies in the design stage. The authors carried out a systematic literature review and identified 10 possible practices that might drive the adoption of agile practices. Those practices were presented to the architectural consultancy firm to identify practices that they are using to successfully adopt agile methods. The findings suggest that maintaining a backlog, running sprints, engaging a cross-functional team, continuous integration, and iterative/incremental development of the design are practices that have enabled the firm to adopt agile methods. Practical and theoretical implications were derived from the findings, and suggestions for future research and limitations of the study are discussed in the discussion. Concluding remarks are provided in final section of the paper.

Two analog computing methods are proposed to compute the continuous-time solutions of one-dimensional (1-D) Maxwell's equations. In the first method, the spatial domain partial derivatives in the governing partial differential equation (PDE) are approximated using discrete finite differences while applying the Laplace transformation along the time dimension. The resulting spatially discrete time-continuous update equation is utilized to design an analog circuit that can compute the continuous-time solution. The second method replaces the discrete-time difference operators in the standard finite difference time domain (FDTD) cell (Yee cell) using continuous-time delay operators, which can be realized using analog all-pass filters. Both methods have been simulated using ideal analog circuits in Cadence Spectre for the Dirichlet, Neumann, and radiation boundary conditions. The performance of the proposed methods has been quantified using: i) mean squared differences between the results and fully discrete FDTD simulations and ii) the noise to signal energy ratio. Both methods have been extended to design the analog circuits that compute the continuous-time solution of the 1-D and 2-D wave equations. The 1-D wave equation solver is simulated with a dominant-pole model (which better approximates the non-ideal circuit behavior) along with a propagation delay compensation technique. The experimental results from a simplified board-level low-frequency implementation are also presented. The key challenges toward CMOS implementations of the proposed solvers are identified and briefly discussed with possible solutions.

Software-programmable analog computing is proposed for power- and area-efficient acceleration of computational electromagnetics. All-pass filters are employed to realize a continuous-time finite-difference time-domain (FDTD) algorithm. A CMOS realization of an analog computer (AC) that solves the 1-D wave equation using this time-continuous FDTD algorithm at an equivalent temporal update rate of 625 MHz is reported (180-nm CMOS, chip area of 4 mm², supply voltage =1.8 V, and power =200 mW). The AC operates at up to 30 MHz over 18 discrete spatial points. Analog arithmetic operations (multiply and add) are realized in parallel using op-amps with gain-bandwidth product >500 MHz. Computational grid boundaries can be configured to simulate multiple propagation scenarios. The AC is calibrated using a stochastic optimization algorithm. The normalized mean squared error of the AC varies between -10 and -20 dB within the computational grid. The power- and area-normalized performance of the design improves on earlier integrated ACs by up to three orders of magnitude. The chip is also 26x faster than a C-based software FDTD solver running on an Intel Xeon CPU and 420x faster than CUDA FDTD code running on an NVIDIA GeForce GTX 1080 Ti GPU, albeit at lower accuracy (~6 bits). Finally, the AC is 2.8x faster than a digital systolic array FDTD processor realized using a Xilinx RFSoC ZCU1275 and has 15x better power efficiency (computations/W).

This article describes a single-chip analog computer for solving 1-D wave equations. The chip uses switched-capacitor (SC)-based fully differential analog circuits to build a discrete-time but continuous-valued finite difference solver with spatially programmable wave velocity, selectable boundary conditions, and arbitrary input excitation waveforms. Correlated double sampling (CDS) and auto-zero techniques are utilized to minimize the offset and low-frequency noise of the op-amps. Built-in third-order Δ- Σ modulators allow the analog solution to be easily read out by a digital processor. The design was realized in TSMC 180-nm CMOS and has an active area of 3.596 mm ×3.131 mm. The solver consumes 560 mW while providing a dynamic range (DR) of 41 dB and a computational bandwidth of either 2.5 MHz (if limited by the analog core) or 0.25 MHz (if limited by the on-chip modulators). Normalized mean squared solution errors for a typical problem (uniform medium with radiation boundary condition) range from 0.3% to 2% (-25 to -17 dB). Measured simulation times are 21×, 5×, and 1.3× faster than CUDA-C code running on a modern GPU (NVIDIA GTX 1080 Ti) and MATLAB or C code running on an 8-core CPU (Intel Xeon Silver 4110 at 2.10 GHz), respectively.

A general-purpose analog computing method is proposed to compute the continuous-time solutions of nonlinear partial differential equations (PDEs). The discrete-time difference operator in the standard finite difference time domain (FDTD) method is replaced by continuous-time delay operators that can be realized using analog all-pass filters. The resulting spatially discrete time-continuous (SDTC) update equations are realized using analog circuits which compute continuous-time solutions of the PDE with prescribed initial and boundary conditions. The proposed concept is demonstrated in simulation via an integrated circuit (IC) design of a nonlinear acoustic wave equation solver in 180 nm CMOS technology. Analog arithmetic operations (multiply, scale, and add) are realized in parallel using fully differential op-amps and analog multipliers. The proposed IC computes the PDE solution in parallel at 33 discrete spatial points and has a simulated bandwidth and power consumption of approximately 2 MHz and 3 W, respectively. The performance of the IC is simulated using foundry-supplied device models and quantified using i) the mean squared difference between the circuit simulation results and FDTD simulations, and ii) the noise to signal energy ratio. Acceptable accuracy is obtained, with error metric values varying between -7 and -30 dB for various configurations of the problem. Comparison of the custom analog IC simulations with MATLAB- and C-based FDTD code running on a modern workstation shows an expected average speedup of 205× and 140×, respectively.

Since the 1960s, the world has witnessed the rise of several East Asian nations as economic powerhouses. One of the main contributing factors of their success is their decision to create policies that allowed them to enter high-tech global production networks. Today, other countries are attempting to do the same by replicating the success of these East Asian nations, but they have had considerably less success. Thus, a study that investigates the drivers of developing countries entering global production networks would be of great use to policymakers in other countries. Hence, with the support of evidence from Vietnam, Malaysia, and Taiwan, this study proposes policy options (government support, science parks, tax, and other incentives, high- and semi-skilled labor, infrastructure development roadmaps, and free trade agreements) that are necessary to initiate and drive the entrance of a developing country into high-tech global production networks. Government support was identified as the main driver that determines the outcome of an effort to enter. Infrastructure development roadmap and free trade agreements were identified as optional. However, it is recommended that governments consider the two optional factors during policy formation, as they could complement the other factors.