The erase operation for the multiple strings of the ferroelectric (Fe)-NAND flash memory is investigated. To achieve the selective erase operation in the Fe-NAND flash memory, the proposed scheme applied the gate induced drain leakage (GIDL) erase method of charge trap flash (CTF) memory for the inhibited strings of the unselected bit line (BL). In addition, the inhibited string of the selected BL remains in a floating state by using the program inhibit scheme of CTF memory. Leaving the unselected word lines (WLs) in a floating state reduces the electrostatic potential difference between the channel and WLs, which in turn suppresses the polarization change of the hafnium oxide (HfO ₂ ) in the inhibited memory cells. The electrostatic potential and polarization of the selected and inhibited strings and the threshold voltage ( V_th ) of each memory cell were analyzed to confirm the success of the selective erase operation. In contrast to the block erase operation of the CTF memory, the Fe-NAND flash memory enables selective erase operation with an operation voltage lowered to 10 V.

This study analyzed the recovery of channel potential according to the program states of adjacent cells. When the verify operation ended, and all voltages dropped to 0 V and the decreased potential of the floating channel caused by the down-coupling phenomenon was recovered continuously over time, regardless of the program states of adjacent WLs. The extent of channel potential recovery showed a similar tendency to that of the variation in the electron concentration of the floating channel. The electron–hole pair recombination decreased the electron concentration, resulting in channel potential recovery. When the adjacent WLs were programmed in a low state, additional electron–hole pair recombination and hole diffusion occurred in the floating channel. Therefore, the channel potential recovered quickly when the adjacent WLs programmed in a low state compared to when they programmed in a high state.

This paper proposes an optimized program operation method for ferroelectric NAND (FE-NAND) flash memory utilizing the gate-induced drain leakage (GIDL) program and validated through simulations. The program operation was performed by setting the time for the unselected cell to reach the pass voltage (V_pass) to 0.1 µs, 0.2 µs, and 0.3 µs, respectively. As the time for the unselected word line (WL) to reach V_pass increases, the channel potential increases due to a decrease in the electron–hole recombination rate. After the program operation, the threshold voltage (V_th) shift of the selected cell and the pass disturb of the unselected cells according to the V_pass condition were analyzed. Consequently, there was a more significant change in V_th among selected cells compared to the time for unselected cells to reach V_pass as 0.1 µs. The findings of this study suggest an optimal program operation that increases slowly and decreases rapidly through the variation of V_th according to the program operation. By performing the proposed program operation, we confirmed that low-power operation is achievable by reducing the WL voltage by 2 V and the bit line (BL) voltage by 1 V, in contrast to the conventional GIDL program.

This study presents a compact model for threedimensional (3D) NAND flash memory that incorporates ferroelectric properties to enable accurate circuit-level simulations. The model, implemented in Verilog-A, captures the saturation polarization-electric field (P-E) hysteresis behavior of a ferroelectric capacitor. To validate the model, simulation results are compared between TCAD and SPICE. Under identical programming conditions, the proposed oxide/nitride/ferroelectric (O/N/F) structure demonstrates approximately 3 V higher channel potential than the conventional oxide/nitride/oxide (O/N/O) structure, resulting in improved programming accuracy and cell stability. In addition, SPICE simulations run over an hour faster than TCAD, making the model efficient for circuit-level analysis.