Porous pads used during the chemical mechanical polishing are critical in IC fabrication for achieving consistent throughput. The hardness of thermoplastic polyurethane pads is identified as a crucial parameter in calibrating the amount of material removed during the polishing process. Through micro-CT scanning technology, a three-dimensional micro-topography model of polyurethane IC1000 pad was developed. Nanoindentation measurements were conducted to evaluate the physical properties of IC1000 pad in the manufacture process. In order to investigate the Vickers hardness of the polyurethane IC1000 pad, which widely use in the fabrication of semiconductor manufacturing, the finite element method was employed to simulate the indentation between Vickers indenter diamond tip and the model of IC1000 pad. This study is not only successfully calibrating the Vickers hardness of polyurethane IC1000 pad with a 3 percent error compared to experimental verification, but also developed a novel methodology for investigating the micro-topography structure of polymer foam materials.

Thin-film copper offers excellent film texture for multilevel interconnections in integrated circuit fabrication due to its superior resistance to electromigration and high electrical conductivity. To perform a chemical mechanical planarization process during semiconductor fabrication of copper, it is necessary to have a thorough understanding of the nanomechanical properties of thin-film copper. In this study, thin-film copper and reacted passivation layers on silicon substrate wafers are investigated for their nanomechanical properties under various environmental conditions. The results of this study indicate that thin-film copper passivation layers have different properties in deionized (DI) water and polishing slurry environments compared to thin-film copper exposed to ambient air. Interestingly, variations in temperature within wet environments do not significantly affect the properties of thin-film copper wafers; but changes in properties are largely driven by chemical processes. The insights gained from this study emphasize the significance of considering both the passivation layers and wet environments in semiconductor fabrication processes, which contributes to the advancement of copper-based interconnect materials and optimization of the chemical mechanical planarization process in semiconductor manufacturing.