The all-sputtered Al/SiO₂/p-GaN metal-oxide-semiconductor (MOS) Schottky diode was fabricated by the cost-effective radio-frequency sputtering technique with a cermet target at 400 °C. Using scanning electron microscope (SEM), the thicknesses of the electrodes, insulator SiO₂ layer, and p-GaN were found to be ~250 nm, 70 nm, and 1 µm, respectively. By Hall measurement of a p-Mg-GaN film on an SiO₂/Si (100) substrate at room temperature, the hole’s concentration (N_p) and carrier mobility (μ) were found to be N_p = 4.32 × 10¹⁶ cm⁻³ and μ = 7.52 cm²·V⁻¹·s⁻¹, respectively. The atomic force microscope (AFM) results showed that the surface topography of the p-GaN film had smoother, smaller grains with a root-mean-square (rms) roughness of 3.27 nm. By I–V measurements at room temperature (RT), the electrical properties of the diode had a leakage current of ~4.49 × 10⁻⁸ A at −1 V, a breakdown voltage of −6 V, a turn-on voltage of ~2.1 V, and a Schottky barrier height (SBH) of 0.67 eV. By C–V measurement at RT, with a frequency range of 100–1000 KHz, the concentration of the diode’s hole increased from 3.92 × 10¹⁶ cm⁻³ at 100 kHz to 5.36 × 10¹⁶ cm⁻³ at 1 MHz, while the Fermi level decreased slightly from 0.109 to 0.099 eV. The SBH of the diode at RT in the C–V test was higher than in the I–V test because of the induced charges by dielectric layer. In addition, the ideality factor (n) and series resistance (R_s) determined by Cheung’s and Norde’s methods, other parameters for MOS diodes were also calculated by C–V measurement at different frequencies.

The modeling of p–In_xGa_1−xN/n–Si hetero junction diodes without using the buffer layer were investigated with the “top-top” electrode. The p–Mg-GaN and p–Mg-In_0.05Ga_0.95N were deposited directly on the n–Si (100) wafer by the RF reactive sputtering at 400 °C with single cermet targets. Al and Pt with the square size of 1 mm² were used for electrodes of p–In_xGa_1−xN/n–Si diodes. Both devices had been designed to prove the p-type performance of 10% Mg-doped in GaN and InGaN films. By Hall measurement at the room temperature (RT), the holes concentration and mobility were determined to be N_p = 3.45 × 10¹⁶ cm⁻³ and µ = 145 cm²/V·s for p–GaN film, N_p = 2.53 × 10¹⁷ cm⁻³, and µ = 45 cm²/V·s for p–InGaN film. By the I–V measurement at RT, the leakage currents at −5 V and turn-on voltages were found to be 9.31 × 10⁻⁷ A and 2.4 V for p–GaN/n–Si and 3.38 × 10⁻⁶ A and 1.5 V for p–InGaN/n–Si diode. The current densities at the forward bias of 20 V were 0.421 and 0.814 A·cm⁻² for p–GaN/n–Si and p–InGaN/n–Si devices. The electrical properties were measured at the temperature range of 25 to 150 °C. By calculating based on the TE mode, Cheungs’ and Norde methods, and other parameters of diodes were also determined and compared.

Thin-film copper offers excellent film texture for multilevel interconnections in integrated circuit fabrication due to its superior resistance to electromigration and high electrical conductivity. To perform a chemical mechanical planarization process during semiconductor fabrication of copper, it is necessary to have a thorough understanding of the nanomechanical properties of thin-film copper. In this study, thin-film copper and reacted passivation layers on silicon substrate wafers are investigated for their nanomechanical properties under various environmental conditions. The results of this study indicate that thin-film copper passivation layers have different properties in deionized (DI) water and polishing slurry environments compared to thin-film copper exposed to ambient air. Interestingly, variations in temperature within wet environments do not significantly affect the properties of thin-film copper wafers; but changes in properties are largely driven by chemical processes. The insights gained from this study emphasize the significance of considering both the passivation layers and wet environments in semiconductor fabrication processes, which contributes to the advancement of copper-based interconnect materials and optimization of the chemical mechanical planarization process in semiconductor manufacturing.