Atrial Fibrillation (AF) is one of the most common heart arrhythmias. It is known to cause up to 15% of all strokes. In current times, modern detection systems for arrhythmias, such as single-use patch electrocardiogram (ECG) devices, have to be energy efficient, small, and affordable. In this work, specialized hardware accelerators were developed. First, an artificial neural network (NN) for the detection of AF was optimized. Special attention was paid to the minimum requirements for the inference on a RISC-V-based microcontroller. Hence, a 32-bit floating-point-based NN was analyzed. To reduce the silicon area needed, the NN was quantized to an 8-bit fixed-point datatype (Q7). Based on this datatype, specialized accelerators were developed. Those accelerators included single-instruction multiple-data (SIMD) hardware as well as accelerators for activation functions such as sigmoid and hyperbolic tangents. To accelerate activation functions that require the e-function as part of their computation (e.g., softmax), an e-function accelerator was implemented in the hardware. To compensate for the losses of quantization, the network was expanded and optimized for run-time and memory requirements. The resulting NN has a 7.5% lower run-time in clock cycles (cc) without the accelerators and 2.2 percentage points (pp) lower accuracy compared to a floating-point-based net, while requiring 65% less memory. With the specialized accelerators, the inference run-time was lowered by 87.2% while the F1-Score decreased by 6.1 pp. Implementing the Q7 accelerators instead of the floating-point unit (FPU), the silicon area needed for the microcontroller in 180 nm-technology is below 1 mm${}^2$.

Objective. In recent years, wearable devices such as smartwatches and smart patches have revolutionized biosignal acquisition and analysis, particularly for monitoring electrocardiography (ECG). However, the limited power supply of these devices often precludes real-time data analysis on the patch itself. Approach. This paper introduces a novel Python package, tinyHLS (High Level Synthesis), designed to address these challenges by converting Python-based AI models into platform-independent hardware description language code accelerators. Specifically designed for convolutional neural networks, tinyHLS seamlessly integrates into the AI developer’s workflow in Python TensorFlow Keras. Our methodology leverages a template-based hardware compiler that ensures flexibility, efficiency, and ease of use. In this work, tinyHLS is first-published featuring templates for several layers of neural networks, such as dense, convolution, max and global average pooling. In the first version, rectified linear unit is supported as activation. It targets one-dimensional data, with a particular focus on time series data. Main results. The generated accelerators are validated in detecting atrial fibrillation on ECG data, demonstrating significant improvements in processing speed (62-fold) and energy efficiency (4.5-fold). Quality of code and synthesizability are ensured by validating the outputs with commercial ASIC design tools. Significance. Importantly, tinyHLS is open-source and does not rely on commercial tools, making it a versatile solution for both academic and commercial applications. The paper also discusses the integration with an open-source RISC-V and potential for future enhancements of tinyHLS, including its application in edge servers and cloud computing. The source code is available on GitHub: https://github.com/Fraunhofer-IMS/tinyHLS

Cardiovascular diseases (CVDs) are currently one of the leading causes of death worldwide. Being able to detect their symptoms at early stages, even the most hidden ones, is crucial to shorten the diagnosis time and facilitate an early treatment. Currently, the use of continuous tracking systems, mainly based on wearable devices that analyze data using artificial intelligence (AI) algorithms, is being explored to automatically identify, in real time, CVDs symptoms. This could be especially relevant in lowincome countries where there is a shortage of specialized doctors. Therefore, this work focuses on analyzing the real-time execution of the state-of-the-art convolutional neural network (CNN) for heart sound segmentation (HSS) on platforms such as traditional CPU/GPU and the Fraunhofer IMS © AIRISC Core Complex (a RISC-V processor developed for AI). Results revealed that, while all implementations exploiting the CPU/GPU platform proved to be useful in real-time diagnosis from a fixed location, the AIRISC demonstrated its goodness, as a system on a chip (SoC) for a real-time wearable application, when executing a quantized version of the CNN.

Processing biomedical signals using artificial intelligence (AI) algorithms, particularly convolutional neural networks (CNNs), presents challenges for resource-limited systems, such as smart patches. For instance, screening electrocardiogram (ECG) signals for heart arrhythmias, including atrial fibrillation (AF), is crucial for enhancing early diagnosis, as this condition is closely linked to an increased risk of stroke and overall mortality. Common approaches for System-on-Chip (SoC) implementation typically involve either a software-based solution utilizing a standard microcontroller or a dedicated hardware accelerator designed to execute the full CNN. This study investigates an approach utilizing reconfigurable fabric, including a theoretical model for efficiency estimation, similar to field programmable gate arrays (FPGAs). These specialized field programmable neural arrays (FPNAs) incorporate specialized tiles designed for AI inference. For instance, in the case of a single convolution, the FPNA occupies only half the silicon area while maintaining equivalent timing performance and achieving a 52.9 % reduction in energy consumption per inference. Further results are presented for a test CNN and a CNN for ECG processing. Although the FPNA may require more area and, at times, more energy per inference than a direct hardware implementation, this trade-off is deemed acceptable due to the advantages of reconfigurability.