The Internet of Things (IoT) plays an important role in all aspects of production and day-to-day life. However, owing to the frequently trusted authentication vulnerabilities, the physical unclonable function (PUF) has unique advantages in the field of equipment authentication because of its nonstorage and nonvolatility. Nevertheless, PUFs are vulnerable to machine learning (ML) attacks. Once a model is constructed accurately, the secrecy of the PUF is lost. Therefore, Bagua matrices are proposed in this study, which can greatly reduce the accuracy of modeling by encrypting the challenge information. On this basis, a whole-process configurable IoT sensing device protocol was constructed for authentication and transmission, and different matrix encryption methods were configured according to the needs of the different devices. Moreover, on the premise of trusted authentication, the perceptual information can be encrypted using a preset matrix. According to the implementation results of the scheme, the resistance to the ML attacks of the PUF improved significantly and the device authentication and encrypted transmission could operate normally.

High-precision miniaturized micromechanical accelerometers are used extensively in the civilian and military fields. A novel self-test-on-chip method and time-multiplexing feedback method for capacitive accelerometers were proposed in this work. The self-test-on-chip circuit can simulate an acceleration signal to test the harmonic distortion without a high-precision shaker table. Using digital timing control, the time-multiplexing feedback can reduce the coupling between the feedback signal and the detection signal. In addition, a low-noise charge sensing and sigma-delta modulator were designed for a high-precision digital output. The interfaced circuit with fully differential topology was fabricated in a 0.35 $\mu $ m standard complementary metal-oxide semiconductor (CMOS) process. The integrated accelerometers can achieve a power consumption of 7 mW from a 5 V supply at a sampling frequency of 256 kHz, a noise floor of $-$ 140 dBV below 400 Hz. The equivalent input noise voltage density is 250nV/ $\surd $ Hz, corresponding to a reference voltage of 2.5V. It can achieve an equivalent noise acceleration of 0.14 $\mu $ g $\surd $ Hz and a bias instability of 9 $\mu $ g at a bandwidth of 400 Hz, a nonlinearity of 0.13% within $\pm$ 1 g.

The physical unclonable function (PUF) can generate a unique identifier for each chip, ideal for key generation and chip anti-counterfeiting. The reliability of PUF is paramount, and therefore is one of the significant challenges for PUF design. This paper proposes a novel SRAM-and Inverter-based PUF (SI PUF) that can operate as either an SRAM PUF or an inverter PUF, depending on the input configuration signal. A zero-overhead bit configuration strategy (BCS) is proposed to enhance the reliability of PUF. Moreover, the working voltage of the sub-threshold level and the well-designed discharge stage ensure that our SI PUF can operate with low power consumption. The tested results of chips fabricated in 40-nm CMOS show that our SI PUF has only 0.0053% of the worst bit error rate (BER) under working conditions of -50 to 125∘C and 0.75 to 1.5V, with 0.073/0.042 pJ/bit of power consumption. The low BER and energy overhead illustrate that our SI PUF is more suitable for resource-limited devices compared to DAC 2022 and JSSC 2020.

The micro-magnetometers with high-resolution digital output are widely used in military and civilian fields. We proposed a novel high-precision interface circuit with optimized chopper technique and switched-capacitor modulator for tunneling magnetoresistance (TMR) sensors. This work also proposes a novel method to create lightweight physically unclonable function (PUF) by using existing TMR devices. The sigma-delta modulator converts the sensor signal into a robust digital output and maintain the signal-to-noise ratio (SNR) of the front-end circuit. We also take advantage of inherent variations of TMR sensors to generate PUF responses that are similarly unique and unclonable. The interface circuit is fabricated by 0.35μm CMOS process from Shanghai Huahong foundry. The active area of ASIC is only about 3 mm×2.7 mm. The interface circuit can achieve a SFDR of 120dB and a SNR of 98 dB at a sampling frequency of 200kHz. The TMR magnetometers were tested in an environment of three-layer magnetic shielding. Our proposed PUF is also tested in terms of uniqueness and reliability.

This article presents a novel class of bistable physically unclonable functions (PUFs) for security-oriented applications. The traditional cross-coupled bistable PUF cell is divided into P-net and N-net, wherein the P-net (N-net) multiplexing acts as the shared head (foot), and the N-net (P-net) duplicating multiple acts as the PUF cell. The proposed PUF was fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm process with full-custom design. It can parallelly generate 128-bit identifications (IDs) in one clock cycle owing to the random access word-level readout framework. The measurement results show that the randomness and uniqueness of the proposed PUF are consistent with those of the state-of-the-art works. In addition, the proposed PUF has the following features: 1) the PUF cell is composed only of four nMOS transistors with a minimum feature size of 215-F²; 2) the native bit instability at the golden condition (i.e., 1.2 V, 25 °C) with 500 evaluations is only 2.05%, showing a desirable native stability against supply noise; 3) the bit-error-rate dependences of the voltage and temperature are 3.35%/V and 0.011%/°C, respectively, with the voltage varying within the range 1.0-1.4 V and the temperature varying within the range -40 °C to 125 °C; 4) an autocorrelation function of 0.0049 at a 95% confidence level is achieved and is the lowest reported value to date; and 5) the energy efficiency and throughput at the maximum operating frequency (i.e., 433 MHz) are 99.48 fJ/b and 55.5 Gb/s, respectively.

This study presents a technique for designing a multimode configurable weak physically unclonable function (PUF) for security-key generation. The PUF cell is based on the maximum gain point deviations of bias-voltage-controlled inverters. By implementing a preselection strategy, the proposed PUF can simultaneously expose all unstable cells under normal voltage and temperature. Owing to the configurable bias circuit, the PUF cell can be biased at three operating modes, namely, traditional inverter (INV), current-starved inverter (CSI), and power gating (PG). The measurement results from a 65-nm prototype show that the proposed PUF has the following outstanding features: 1) it has a compact cell layout with a minimum feature size of 966 F2; 2) an autocorrelation function of 0.0099 is achieved; and 3) all unstable cells can be eliminated using a preselection procedure, which can drastically reduce the energy and area costs for error correction. In addition, in the CSI mode, the proposed PUF (standard voltage) has maximum frequency and throughput of 714 MHz and 45.7 Gb/s, respectively. Meanwhile, under the INV mode, the worst native bit error rate (low voltage) for 5000 evaluations is only 0.33%, indicating a desirable instability against voltage and temperature variations with a sensitivity coefficient of 1.85%/V and 0.018%/°C, respectively. Moreover, the measured energy efficiency at 0.6 V is 6.83 fJ/bit. Finally, under the PG mode, the standby powers at 0.6 and 1.2 V are only 18 and 86 nW, respectively.