We developed a novel technique, selective epitaxial lateral overgrowth (ELO), to fabricate a local but sufficiently large silicon-on-insulator (SOI) platform on conventional silicon wafers. Based on high-level crystallinity of the local SOI, we implemented reconfigurable FETs with three gates. These FETs demonstrate n- and p-type behavior depending on the applied bias. Not only the reconfigurable FETs but also their logic gates (inverter and NAND) delivered sound performance. Using a compact model based on the surface potential of the channel, we derived the key parameters of the proposed reconfigurable FET and used the model to explain the peculiarities in its working behavior. Owing to the unique advantages of a local SOI, reconfigurable FETs can be seamlessly incorporated into a silicon platform as a building block for CMOS-SOI hybrid electronics.

Recent research on transistors has focused on gate-all-around (GAA) structures, which possess better gate controllability than previous fin field-effect transistor (FinFET) structures. The characteristics of these devices have been optimized through different channel shapes. However, the characteristics of GAA-FETs with channels that have the same cross-sectional area warrant further research. In this study, we simulated n-type GAA-FETs using the Global TCAD Solutions simulation tool to analyze the effective characteristics obtained by setting equal cross-sectional areas. The results show that the total on-current exhibited up to 40.5% enhancement based on shape for the same area. Similarly, under the same conditions, the on/off current ratio exhibited a difference of approximately 1.5 times based on the shape. These findings help determine the optimal shape of the GAA channel and predict the performance when physical limitations restrict the channel shape. Furthermore, they contribute to improving the characteristics of GAA-FETs in mass production.

Batch normalization (BN) is a technique used to enhance training speed and generalization performance by mitigating internal covariate shifts. However, implementing BN in hardware presents challenges due to the need for an additional complex circuit to normalize, scale and shift activations. We proposed a hardware binary neural network (BNN) system capable of BN in hardware, which is consist of an AND-type flash memory array as a synapse and a voltage sense amplifier (VSA) as a neuron. In this system, hardware BN was implemented using a voltage shifter by adjusting the threshold of the binary neuron. To validate the effectiveness of the proposed hardware-based BNN system, we fabricated a charge trap flash with a gate stack of SiO ₂ /Si ₃ N ₄ /SiO ₂ . The electrical characteristics were modelled by using BSIM3 model parameters so that the proposed circuit was successfully demonstrated by a SPICE simulation. Moreover, variation effects of the voltage shifter were also analyzed using Monte Carlo simulation. Finally, the performance of the proposed system was proved by incorporating the SPICE results into a high-level simulation of binary LeNet-5 for MNIST pattern recognition, resulting in the improvement of the proposed system in terms of power and area, compared to the previous studies.

Based on the analysis of the carrier density change of a symmetric gate reconfigurable field‐effect transistor that can operate p‐ or n‐type transistors in an integrated circuit (IC), its unique limiting factor, carrier build‐up time, is quantitatively derived for operating speed in addition to conventional resistance and capacitance (RC) and transit time effect. Originating from the characteristic of carrier confinement in a channel between two Schottky potential barriers, the carrier build‐up time for the operation could take up to ∼1000 times longer than the transit time across the channel.