Homeothermic synaptic behaviors with a wide range of temperature were demonstrated in CMOS-compatible HfO _x /AlO _y memristors.

In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry and academia and adopted in commercial mass production. In this paper, 3D NAND flash technologies are reviewed in terms of their architecture and fabrication methods, and the advantages and disadvantages of the architectures are compared.

A neuromorphic system is composed of hardware-based artificial neurons and synaptic devices, designed to improve the efficiency of neural computations inspired by energy-efficient and parallel operations of the biological nervous system. A synaptic device-based array can compute vector–matrix multiplication (VMM) with given input voltage signals, as a non-volatile memory device stores the weight information of the neural network in the form of conductance or capacitance. However, unlike software-based neural networks, the neuromorphic system unavoidably exhibits non-ideal characteristics that can have an adverse impact on overall system performance. In this study, the characteristics required for synaptic devices and their importance are discussed, depending on the targeted application. We categorize synaptic devices into two types: conductance-based and capacitance-based, and thoroughly explore the operations and characteristics of each device. The array structure according to the device structure and the VMM operation mechanism of each structure are analyzed, including recent advances in array-level implementation of synaptic devices. Furthermore, we reviewed studies to minimize the effect of hardware non-idealities, which degrades the performance of hardware neural networks. These studies introduce techniques in hardware and signal engineering, as well as software-hardware co-optimization, to address these non-idealities through compensation approaches.

We perform a system-level simulation of hardware spiking neural network (SNN) consisting of silicon-based synaptic transistors and integrate-and-fire (I&F) neuron circuits. Using electrical models of the synaptic device and I&F neuron circuit, a three-layer fully connected SNN in hardware is presented for MNIST pattern recognition by means of ex situ training. Right-justified rate coding is employed as an information encoding method, and negative weight values are implemented by a pair of the synaptic transistors (specifically, excitatory and inhibitory synapses). Furthermore, the variability effect occurring in the devices and circuits is demonstrated. This result indicates that the system has tolerance to the variations and how precisely the variations need to be controlled for hardware SNN applications.

In this work, we present a hardware neural network with capacitor-based synaptic devices. A capacitor-based synaptic device was developed using a MOS capacitor structure with a charge trapping layer. Due to the flat band voltage shift by charge trapping and its non-linear ${C} - {V}$ characteristics, multilevel weight values could be implemented by the charge occurring when charging and discharging the capacitor. The vector-matrix multiplication (VMM) function was also experimentally verified using a fabricated synapse array based on NAND flash structure.

Ferroelectric field-effect transistor (FeFET) can be operated as a nonvolatile memory device with low programming voltage based on polarization. In particular, it can be used as a synaptic device in a neuromorphic system based on the nand flash array structure. We demonstrate a Hf $_\text{0.5}$ Zr $_\text{0.5}$ O $_\text{2}$ (HZO)-based FeFET device fabricated on a silicon-on-insulator (SOI) substrate with high on/off ratio and reliability characteristics. The HZO-based FeFET is utilized as a synaptic device based on the 3-D nand architecture. It is verified with the binarization of input–output signals and weight value for efficient vector–matrix multiplication (VMM) operation using the 3-D nand architecture. In addition, a neural network layer-mapping method increasing synaptic cell efficiency is proposed. A system-level simulation is performed based on the FeFET single-device experimental data. The VMM operation is verified through the SPICE Berkeley short-channel IGFET model (BSIM), and off-chip ( ex-situ ) learning with binary neural network (BNN) is performed for the Modified National Institute of Standards and Technology Database MNIST and fashion-MNIST data. The results confirm that the proposed FeFET-based BNN can perform accurate VMM operations and is robust to variations due to the binary weight state.