A Fabry-Pérot cavity (FPC) antenna producing both high-gain and circularly-polarized (CP) behavior is proposed. To increase antenna gain and obtain CP characteristics, a superstrate composed of square patches with a pair of truncated corners is placed above the linearly polarized patch antenna with an approximately half-wavelength distance from the ground plane at the operating frequency. The proposed antenna has the advantages of high gain, a simple design, and an excellent boresight axial ratio over the operating frequency bandwidth. Moreover, used in an FPC antenna, the proposed superstrate converts a linear polarization produced by a patch antenna into a circular polarization. In addition, the cavity antenna produces left-hand circular-polarization and right-hand circular-polarization when a patch antenna inside the cavity generates x-direction and y-direction polarization, respectively. The measured and simulated results verify the performance of the antenna.

In this paper, we propose a smart insole for inexpensive plantar pressure sensing and a simple visualizing scheme. The insole is composed of two elastomeric layers and two electrode layers where the common top electrode is submerged in the insole. The upper elastomeric layer is non-conductive poly-dimethyl-siloxane (PDMS) and supports plantar pressure buffering and the lower layer is carbon nano-tube (CNT)-dispersed PDMS for pressure sensing through piezo-resistivity. Under the lower sensing layer are 16 bottom electrodes for pressure distribution sensing without cell-to-cell interference. Since no soldering or sewing is needed the smart insole manufacturing processes is simple and cost-effective. The pressure sensitivity and time response of the material was measured and based on the 16 sensing data of the smart insole, we virtually extended the frame size for continuous and smoothed pressure distribution image with the help of a simple pseudo interpolation scheme.

Batch normalization (BN) is a technique used to enhance training speed and generalization performance by mitigating internal covariate shifts. However, implementing BN in hardware presents challenges due to the need for an additional complex circuit to normalize, scale and shift activations. We proposed a hardware binary neural network (BNN) system capable of BN in hardware, which is consist of an AND-type flash memory array as a synapse and a voltage sense amplifier (VSA) as a neuron. In this system, hardware BN was implemented using a voltage shifter by adjusting the threshold of the binary neuron. To validate the effectiveness of the proposed hardware-based BNN system, we fabricated a charge trap flash with a gate stack of SiO ₂ /Si ₃ N ₄ /SiO ₂ . The electrical characteristics were modelled by using BSIM3 model parameters so that the proposed circuit was successfully demonstrated by a SPICE simulation. Moreover, variation effects of the voltage shifter were also analyzed using Monte Carlo simulation. Finally, the performance of the proposed system was proved by incorporating the SPICE results into a high-level simulation of binary LeNet-5 for MNIST pattern recognition, resulting in the improvement of the proposed system in terms of power and area, compared to the previous studies.