Finite-field arithmetic operations are vital for the computation of complex cryptography algorithms used in several cutting-edge applications, such as side-channel attacks, authentication, digital signatures, among others. Currently, the simulation of these algorithms exceeds the computational capabilities of conventional computing systems. This aspect becomes critical, especially when these algorithms are implemented in resource-constrained electronic appliances. In particular, the improvement of execution time in these devices generally require more area. To overcome this issue, a large number of works have been focused on the development of compact conventional binary finite-field arithmetic circuits over GF(p) since these demand a large area consumption. Inspired by neural phenomena, a new emerging branch of computer science has made intensive efforts to improve area consumption of conventional arithmetic circuits. However, the development of compact finite-field arithmetic circuits over GF(p) is a still a challenging task. In this work, we present for the first time, the design of four new finite-field arithmetic circuits over GF(p) based on spiking neural P (SN P) systems with communication on request. In addition, we propose a neural processor to perform four new finite-field arithmetic operations over GF(p) by using the same processing core, which is not feasible with the use of conventional binary circuits since each finite-field arithmetic-binary circuit over GF(p) is implemented separately, to significantly improve the area consumption. This has mainly been achieved since the neural processor dynamically change its configuration, which is defined in terms of the connectivity and firing rules of each neuron.

During the last five years, spiking neural P (SN P) systems have attracted a lot of attention in the field of cryptography since these systems can more efficiently support advanced and complex cryptographic algorithms due to their high computational capabilities. Specifically, these systems can be seen as a potential solution to efficiently performing asymmetric algorithms, which are more demanding than symmetric systems. This factor becomes critical, especially in resource-constrained single-board computer systems, since many of these systems are currently used to ensure the security of IoT applications in portable systems. In this work, we present for the first time the implementation of an asymmetric encryption algorithm called ElGamal based on spiking neural P systems and their cutting-edge variants. The proposed design involves the encryption and decryption processes. Specifically, we propose the design of a neural network to efficiently perform the extended Euclidean algorithm used in the decryption task. Here, we exert major efforts to create a compact and high-performance circuit to perform the extended Euclidean algorithm since the calculation of this algorithm is the most demanding when the decryption process is required. Finally, we perform several tests to show the computational capabilities of our proposal in comparison to conventional implementations on single-board computer systems. Our results show that the proposed encryption/decryption scheme potentially allows its use to ensure confidentiality, data integrity, and secure authentication, among other applications for resource-constrained embedded systems.

During the last years, the demand for internet-of-things (IoT) resource-constrained devices has grown exponentially. To address this need, several digital methods have been proposed to improve these devices in terms of area and power consumption. Despite achieving significant results, improvement in these factors is still a challenging task. Recently, an emerging computational area has been seen as a potential solution to improving the performance of conventional binary circuits. In particular, this area uses a method based on spiking neural P systems (SN P) to create arithmetic circuits, such as adders, subtractors, multipliers, and divisors, since these components are vital in many IoT applications. To date, several efforts have been dedicated to decreasing the number of neurons and synapses to create compact circuits. However, processing speed is a persistent issue. In this work, we propose four compact arithmetic circuits with high processing speeds. To evaluate their performance, we designed a neuromorphic processor that is capable of performing four operations using dynamic connectivity. As a consequence, the proposed neuromorphic processor achieves higher processing speeds by maintaining low area consumption in comparison with the existing approaches.