Elliptic curve scalar multiplication (ECSM) is the essential operation in elliptic curve cryptography (ECC) for achieving high performance and security. We introduce a novel high-performance ECSM architecture over binary fields to meet the growing demand for performance and security. A low-latency window (LLW) recoding algorithm for hardware implementation is proposed to enhance the resistance toward side-channel attacks (SCAs). Based on the LLW algorithm, we propose an enhanced comb method for ECSM with a unified point addition (PA) and point doubling (PD) pattern. The theoretical analysis demonstrates that the enhanced comb method with $w=4$ strikes the balance of computation burden for both extreme cases. To achieve short clock cycle latency and high frequency, the data dependency of ECSM is thoroughly analyzed, and we explore a timing schedule with one two-stage pipelined Karatsuba multiplier accumulator (MAC). The datapath of the proposed architecture is well-designed, ensuring that the critical path (CP) only contains minimal logic primitives apart from the MAC. Besides, the ideal placement of pipeline stages for MAC is illustrated. The proposed architecture has been implemented on Xilinx Virtex-7 series field-programmable gate arrays (FPGAs) and performs ECSM in 2.51, 4.93, and $10.85 ~\mu \text { s}$ with 3422, 7983, and 20158 slices over $\text {GF}(2^{163})$ , $\text {GF}(2^{283})$ , and $\text {GF}(2^{571})$ , respectively. Implementation results reveal that our design shows 53.60%, 39.36%, and 32.64% performance improvement over the existing state-of-the-art works, respectively.

Modular multiplication is a crucial operation in public-key cryptography systems such as RSA and ECC. In this study, we analyze and improve the iteration steps of the classic Montgomery modular multiplication (MMM) algorithm and propose an interleaved pipeline (IP) structure, which meets the high-performance and low-cost requirements for Internet of Things devices. Compared to the classic pipeline structure, the IP does not require a multiplexing processing element (PE), which helps shorten the data path of intermediate results. We further introduce a disruption in the critical path to complete an iterative step of the MMM algorithm in two clock cycles. Our proposed hardware architecture is implemented on Xilinx Virtex-7 Series FPGA, using DSP48E1, to realize the multiplier. The implemented results show that the modular multiplication of 1024 bits by 2048 bits requires 1.03 $\mathsf{\mu }$s and 2.13 $\mathsf{\mu }$s, respectively. Moreover, our area–time–product analysis reveals a favorable outcome compared to the state-of-the-art designs across a 1024-bit and 2048-bit modulus.

Modular multiplication is one of the key operations in modern public-key cryptography. Montgomery Modular Multiplication (MMM) is a mainstream method to avoid modulo operations, which contains one variable multiplication and two constant multiplications. In this paper, for high performance, a novel Hybrid Truncated Montgomery Modular Multiplication (HTMMM) algorithm and its hardware architecture are proposed, which achieves state-of-the-art Area-Time-Product (ATP) and throughput. We propose an error-free high-part truncated multiplication for the first time, which solves the problem that conventional methods cannot be applied to MMM due to the introduced error, and reduces the complexity to the same level as low-part truncated multiplication. Besides, a hybrid multiplication based on Toom-Cook and Karatsuba is proposed to optimize variable multiplication, Non-Adjacent Form (NAF) encoding is adopted with truncated multiplication to optimize constant multiplications. The quantitative analysis of complexity for the integer multipliers with different schemes are illustrated to find the optimal multiplier under various cases. Based on these, we took the bit width N = 1024 as an example to introduce the hardware architecture in detail and gave the implementation results of N = 256 and N = 1024 in different processes. The experimental results demonstrate that compared with the best existing design, the throughput and ATP of our proposed design are improved by 1.25× and 2.22×, respectively.