In this paper, we present a novel lightweight elliptic curve scalar multiplication architecture for random Weierstrass curves over prime field ${\mathbb{F}}_p$. The elliptic curve scalar multiplication is executed in Jacobian coordinates based on the Montgomery ladder algorithm with (X,Y)-only common Z coordinate arithmetic. At the finite field operation level, the adder-based modular multiplier and modular divider are optimized by the pre-calculation method to reduce the critical path while maintaining low resource consumption. At the group operation level, the point addition and point doubling methods in (X,Y)-only common Z coordinate arithmetic are modified to improve computation parallelism. A compact scheduling method is presented to improve the architecture’s performance, which includes appropriate scheduling of finite field operations and specific register connections. Compared with existing works, our design is implemented on the FPGA platform without using DSPs or BRAMs for higher portability. It utilizes 6.4~6.5k slices in Kintex-7, Virtex-7, and ZYNQ FPGA and executes an elliptic curve scalar multiplication for a field size of 256-bit in 1.73 ms, 1.70 ms, and 1.80 ms, respectively. Additionally, our design is resistant to timing attacks, simple power analysis attacks, and safe-error attacks. This architecture outperforms most state-of-the-art lightweight designs in terms of area-time products.

Elliptic curve scalar multiplication (ECSM) is the essential operation in elliptic curve cryptography (ECC) for achieving high performance and security. We introduce a novel high-performance ECSM architecture over binary fields to meet the growing demand for performance and security. A low-latency window (LLW) recoding algorithm for hardware implementation is proposed to enhance the resistance toward side-channel attacks (SCAs). Based on the LLW algorithm, we propose an enhanced comb method for ECSM with a unified point addition (PA) and point doubling (PD) pattern. The theoretical analysis demonstrates that the enhanced comb method with $w=4$ strikes the balance of computation burden for both extreme cases. To achieve short clock cycle latency and high frequency, the data dependency of ECSM is thoroughly analyzed, and we explore a timing schedule with one two-stage pipelined Karatsuba multiplier accumulator (MAC). The datapath of the proposed architecture is well-designed, ensuring that the critical path (CP) only contains minimal logic primitives apart from the MAC. Besides, the ideal placement of pipeline stages for MAC is illustrated. The proposed architecture has been implemented on Xilinx Virtex-7 series field-programmable gate arrays (FPGAs) and performs ECSM in 2.51, 4.93, and $10.85 ~\mu \text { s}$ with 3422, 7983, and 20158 slices over $\text {GF}(2^{163})$ , $\text {GF}(2^{283})$ , and $\text {GF}(2^{571})$ , respectively. Implementation results reveal that our design shows 53.60%, 39.36%, and 32.64% performance improvement over the existing state-of-the-art works, respectively.

Modular multiplication is a crucial operation in public-key cryptography systems such as RSA and ECC. In this study, we analyze and improve the iteration steps of the classic Montgomery modular multiplication (MMM) algorithm and propose an interleaved pipeline (IP) structure, which meets the high-performance and low-cost requirements for Internet of Things devices. Compared to the classic pipeline structure, the IP does not require a multiplexing processing element (PE), which helps shorten the data path of intermediate results. We further introduce a disruption in the critical path to complete an iterative step of the MMM algorithm in two clock cycles. Our proposed hardware architecture is implemented on Xilinx Virtex-7 Series FPGA, using DSP48E1, to realize the multiplier. The implemented results show that the modular multiplication of 1024 bits by 2048 bits requires 1.03 $\mathsf{\mu }$s and 2.13 $\mathsf{\mu }$s, respectively. Moreover, our area–time–product analysis reveals a favorable outcome compared to the state-of-the-art designs across a 1024-bit and 2048-bit modulus.

This paper presents an FPGA-based lightweight and real-time infrared image processor based on a series of hardware-oriented lightweight algorithms. The two-point correction algorithm based on blackbody radiation is introduced to calibrate the non-uniformity of the sensor. With precomputed gain and offset matrices, the design can achieve real-time non-uniformity correction with a resolution of $640\times 480$. The blind pixel detection algorithm employs the first-level approximation to simplify multiple iterative computations. The blind pixel compensation algorithm in our design is constructed on the side-window-filtering method. The results of eight convolution kernels for side windows are computed simultaneously to improve the processing speed. Due to the proposed side-window-filtering-based blind pixel compensation algorithm, blind pixels can be effectively compensated while details in the image are preserved. Before image output, we also incorporated lightweight histogram equalization to make the processed image more easily observable to the human eyes. The proposed lightweight infrared image processor is implemented on Xilinx XC7A100T-2. Our proposed lightweight infrared image processor costs 10,894 LUTs, 9367 FFs, 4 BRAMs, and 5 DSP48. Under a 50 MHz clock, the processor achieves a speed of 30 frames per second at the cost of 1800 mW. The maximum operating frequency of our proposed processor can reach 186 MHz. Compared with existing similar works, our proposed infrared image processor incurs minimal resource overhead and has lower power consumption.

Point multiplication is the core operation in elliptic curve cryptography (ECC). Koblitz curves are a special class of curves that can utilize the Frobenius mapping to accelerate the implementation of point multiplication operations. For point multiplication on Koblitz curves, this article first proposes an optimized tNAF scalar conversion algorithm along with its corresponding hardware architecture. Additionally, for the computation of point multiplication, this article proposes two optimal computational architectures: 1) an area-efficient architecture and 2) a low-latency architecture, both of which achieve the highest pipeline efficiency. The area-efficient architecture adopts a compact four-stage pipeline with a single multiplier, ensuring high circuit area utilization efficiency while achieving relatively low computation latency. The low-latency architecture implements two-stage and three-stage pipeline designs, respectively in different binary fields, using two multipliers to reduce the clock cycles for point addition (PA) and further decrease the computation latency. The proposed architectures were implemented on Virtex-7 FPGA. For the $ 2^{163}$ ), ${\mathrm { GF}}(2^{283})$ , and ${\mathrm { GF}}(2^{571})$ fields, the latency for the area-efficient architecture are $1.683~\mu {\mathrm { s}}$ , $3.455~\mu {\mathrm { s}}$ , and $7.511~\mu {\mathrm { s}}$ , with slices usage of 3631, 7867, and 20612, and the point multiplication latency for the low-latency architecture are $1.347~\mu {\mathrm { s}}$ , $3.279~\mu {\mathrm { s}}$ and $7.071~\mu {\mathrm { s}}$ , with slices usage of 6026, 14246, and 38515. A comparison with state-of-the-art designs shows that the proposed point multiplication architectures offer significant advantages in terms of performance. In the ${\mathrm { GF}}(2^{163})$ field, the computation latency of the area-efficient architecture and the low-latency architecture is reduced by at least 21.158% and 43.952%, respectively. And in the ${\mathrm { GF}}(2^{283})$ field, the reduction in latency is 38.985% and 42.459%, while in the ${\mathrm { GF}}(2^{571})$ field, the reduction in latency is 58.111% and 59.720%.

In recent years, the deep learning method has emerged as a mainstream approach to non-profiled side-channel attacks. However, most existing methods of deep learning-based non-profiled side-channel attack rely on traditional metrics such as loss and accuracy, which often suffer from unclear results in practical scenarios. Furthermore, most previous studies have not fully considered the properties of power traces as long time-series data. In this paper, a novel non-profiled side-channel attack architecture is proposed, which incorporates the attention mechanism and derives a corresponding attention metric. By attaching the attention mechanism after the network layers, the attention mechanism provides a quantitative prediction of correct key. Moreover, this architecture can effectively extract and analyze the features from long power traces. The success rate on different datasets is at least 86%, which demonstrates the superior reliability of this architecture compared to other works when facing various countermeasures and noise. Notably, even in scenarios where traditional loss and accuracy metrics fail to provide reliable results, the proposed attention metric remains capable of accurately distinguishing the correct key.