In this paper, we present a novel lightweight elliptic curve scalar multiplication architecture for random Weierstrass curves over prime field ${\mathbb{F}}_p$. The elliptic curve scalar multiplication is executed in Jacobian coordinates based on the Montgomery ladder algorithm with (X,Y)-only common Z coordinate arithmetic. At the finite field operation level, the adder-based modular multiplier and modular divider are optimized by the pre-calculation method to reduce the critical path while maintaining low resource consumption. At the group operation level, the point addition and point doubling methods in (X,Y)-only common Z coordinate arithmetic are modified to improve computation parallelism. A compact scheduling method is presented to improve the architecture’s performance, which includes appropriate scheduling of finite field operations and specific register connections. Compared with existing works, our design is implemented on the FPGA platform without using DSPs or BRAMs for higher portability. It utilizes 6.4~6.5k slices in Kintex-7, Virtex-7, and ZYNQ FPGA and executes an elliptic curve scalar multiplication for a field size of 256-bit in 1.73 ms, 1.70 ms, and 1.80 ms, respectively. Additionally, our design is resistant to timing attacks, simple power analysis attacks, and safe-error attacks. This architecture outperforms most state-of-the-art lightweight designs in terms of area-time products.

Speech Emotion Recognition (SER) plays a significant role in the field of Human–Computer Interaction (HCI) with a wide range of applications. However, there are still some issues in practical application. One of the issues is the difference between emotional expression amongst various individuals, and another is that some indistinguishable emotions may reduce the stability of the SER system. In this paper, we propose a multi-layer hybrid fuzzy support vector machine (MLHF-SVM) model, which includes three layers: feature extraction layer, pre-classification layer, and classification layer. The MLHF-SVM model solves the above-mentioned issues by fuzzy c-means (FCM) based on identification information of human and multi-layer SVM classifiers, respectively. In addition, to overcome the weakness that FCM tends to fall into local minima, an improved natural exponential inertia weight particle swarm optimization (IEPSO) algorithm is proposed and integrated with fuzzy c-means for optimization. Moreover, in the feature extraction layer, non-personalized features and personalized features are combined to improve accuracy. In order to verify the effectiveness of the proposed model, all emotions in three popular datasets are used for simulation. The results show that this model can effectively improve the success rate of classification and the maximum value of a single emotion recognition rate is 97.67% on the EmoDB dataset.

The Toom-Cook multiplier (TCM) is the most suitable method for multiplying large integers with key widths typically employed in ECC or RSA due to its computational efficiency. In this brief, we improve the accuracy of hardware TCM algorithm, and propose a TCM-based Barrett modular multiplication algorithm. We provide detailed mathematical proofs for the determinantion of parameters, error ranges, and input-output bounds, which serve to validate the robustness and reliability of our proposed algorithm. Further, the hardware architecture and the ASIC implementation results under 40nm, 65nm, 90nm process are presented. Compared with existing works, the proposed modular multiplier exhibits superior performance in terms of Area-Time-Product.

Point multiplication is the core operation in elliptic curve cryptography (ECC). Koblitz curves are a special class of curves that can utilize the Frobenius mapping to accelerate the implementation of point multiplication operations. For point multiplication on Koblitz curves, this article first proposes an optimized tNAF scalar conversion algorithm along with its corresponding hardware architecture. Additionally, for the computation of point multiplication, this article proposes two optimal computational architectures: 1) an area-efficient architecture and 2) a low-latency architecture, both of which achieve the highest pipeline efficiency. The area-efficient architecture adopts a compact four-stage pipeline with a single multiplier, ensuring high circuit area utilization efficiency while achieving relatively low computation latency. The low-latency architecture implements two-stage and three-stage pipeline designs, respectively in different binary fields, using two multipliers to reduce the clock cycles for point addition (PA) and further decrease the computation latency. The proposed architectures were implemented on Virtex-7 FPGA. For the $ 2^{163}$ ), ${\mathrm { GF}}(2^{283})$ , and ${\mathrm { GF}}(2^{571})$ fields, the latency for the area-efficient architecture are $1.683~\mu {\mathrm { s}}$ , $3.455~\mu {\mathrm { s}}$ , and $7.511~\mu {\mathrm { s}}$ , with slices usage of 3631, 7867, and 20612, and the point multiplication latency for the low-latency architecture are $1.347~\mu {\mathrm { s}}$ , $3.279~\mu {\mathrm { s}}$ and $7.071~\mu {\mathrm { s}}$ , with slices usage of 6026, 14246, and 38515. A comparison with state-of-the-art designs shows that the proposed point multiplication architectures offer significant advantages in terms of performance. In the ${\mathrm { GF}}(2^{163})$ field, the computation latency of the area-efficient architecture and the low-latency architecture is reduced by at least 21.158% and 43.952%, respectively. And in the ${\mathrm { GF}}(2^{283})$ field, the reduction in latency is 38.985% and 42.459%, while in the ${\mathrm { GF}}(2^{571})$ field, the reduction in latency is 58.111% and 59.720%.

Toom–Cook-n multiplication is an efficient large-width multiplication algorithm based on a divide-and-conquer strategy, widely used in modular multiplication operations for cryptographic algorithms. Theoretically, as the degree n increases, Toom–Cook-n can split the multiplicands into more sub-terms to further enhance the performance of the multiplier. However, constrained by the computational burden brought by the growing size of the interpolation matrix as the degree increases, current research predominantly focuses on Toom–Cook-4 and Toom–Cook-3. This paper proposes a Montgomery modular multiplication design based on Toom–Cook-5, which alleviates the computational difficulty of the interpolation step by introducing an interpolation matrix pre-simplification strategy. Additionally, the design incorporates and optimizes carry–save adder and Karatsuba multiplication, enabling Toom–Cook-5 multiplication to be applied in practical and efficient hardware implementation. This paper presents the ASIC implementation results of the hardware architecture under a 90nm process, demonstrating superior performance compared to previous works.

Physically unclonable functions (PUFs) are crucial for enhancing cybersecurity by providing unique, intrinsic identifiers for electronic devices, thus ensuring their authenticity and preventing unauthorized cloning. The SRAM-PUF, characterized by its simple structure and ease of implementation in various scenarios, has gained widespread usage. The soft-decision Reed–Muller (RM) code, an error correction code, is commonly employed in these designs. This paper introduces the design of an RM code soft-decision attack algorithm to reveal its potential security risks. To address this problem, we propose a soft-decision SRAM-PUF structure based on the elliptic curve digital signature algorithm (ECDSA). To improve the processing speed of the proposed secure SRAM-PUF, we propose a custom ECDSA scheme. Further, we also propose a universal architecture for the critical operations in ECDSA, elliptic curve scalar multiplication (ECSM), and elliptic curve double scalar multiplication (ECDSM) based on the differential addition chain (DAC). For ECSMs, iterations can be performed directly; for ECDSMs, a two-dimensional DAC is constructed through precomputation, followed by iterations. Moreover, due to the high similarity of ECSM and ECDSM data paths, this universal architecture saves hardware resources. Our design is implemented on a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) using a Xilinx Virtex-7 and an TSMC 40 nm process. Compared to existing research, our design exhibits a lower bit error rate ($2.7\times {10}^{-10}$) and better area–time performance (3902 slices, 6.615 $\mathsf{\mu }$s ECDSM latency).