A vertical channel ferroelectric-FET (FeFET) with HfO ₂ -based ferroelectric (Fe-HfO ₂ ) and atomic layer deposition (ALD) Indium oxide (InOx) channel has been developed and demonstrated for 3D high-density memory applications. Reliable memory operation has been confirmed with memory window (MW) >1V in gate length (L _g ) = 50nm short channel FeFETs. Polar-axis transition of Fe-HfO ₂ from in- plane in the initial film to out-of-plane after electrical cycling has been verified by both experimental and theoretical studies. A vertical channel anti-ferroelectric (AFe) FET (AFeFET) with ZrO ₂ has been also demonstrated by making use of half-loop hysteresis in AFe, which can be a new solution for the weak erase problem seen in oxide semiconductor channel FeFETs.

We have investigated ferroelectric phase formation of Si-doped HfO₂ through nucleation and phase transition in the thermal process by first-principles simulation. For the nucleation process from amorphous HfO₂ in the thin film during thermal annealing, the tetragonal phase can be thermodynamically preferred with the effects of dopant and surface energy and temperature for which entropy is directly calculated from phonon spectrum calculations. During cooling down, the diffusionless phase transition from the tetragonal to ferroelectric phase takes place by atomic displacement and the transition to the monoclinic phase is suppressed by the high kinetic activation barrier. The phase transition process from the tetragonal phase to the ferroelectric phase is directly confirmed by ab initio molecular-dynamics simulation.

We have developed and integrated a mobility-enhanced FET and a wakeup-free ferroelectric (FE) capacitor using Sn-doped InGaZnO (IGZTO) and demonstrated 1T1C FeRAM cell operation for 3-D embedded RAM application. IGZTO FET can achieve >20 cm ² /V $\cdot $ s mobility with an ultrathin channel, which is $2\times $ higher than InGaZnO (IGZO) FET. The physics of mobility enhancement in oxide semiconductor FET with IGZTO channel is investigated by both experimental and simulation methods. The FE capacitor with large remanent polarization and low-temperature process at 400 °C is achieved. We have also studied the impact of thin-film access transistors on 1T1C cell operation with gate voltage dependence and capacitor size dependence. SPICE simulation is used for an extremely scaled device that achieves ~ns operation. The proposed memory technology will enable high-density and energy-efficient computing by the proximity of processor core and memory in monolithic 3-D integration.

We have monolithically integrated resistance random access memory (RRAM) array with oxide semiconductor channel access transistor in 3-D stack, achieved uniform memory characteristics of 1T1R cells at each layer, and demonstrated basic functionality of XNOR operation as in-memory computing for binary neural network (BNN) artificial intelligence (AI) applications. The integrated TiN/Ti/HfO ₂ /Ti stack RRAM shows high on/off ratio with stable retention and endurance properties. The indium gallium zinc oxide (IGZO) channel field-effect transistor (FET) works as an access transistor, which realized the low-temperature process, high mobility, and high drive current for RRAM. With the peripheral circuit, we demonstrate the XNOR operation using a pair of 1T1R cells. The impact of RRAM bit error rate on neural network is also investigated, which indicates the property of error-resilience in BNN. The 3-D neural network built by this architecture has high potential to enable area-efficient, low-power, and low-latency computing.

Reservoir computing (RC) is a low-cost and temporary-signal friendly computational framework, whose hardware implementation is hindered by integrating huge amounts and various kinds of devices. Benefitted from the logic in memory (LIM) capability, the process compatible Hf _0.5 Zr _0.5 O ₂ (HZO)-based ferroelectric field-effect-transistor (FeFET) is a promising candidate for implementing artificial networks. In this letter, a fully FeFETs RC network is proposed. Multiple functions can be achieved in a single device owing to its intrinsic characteristics, and the richness of virtual nodes is largely enhanced through full-connection structures. Impressively, only 44 FeFETs are required to construct a compact RC network with 100 ns operating speed and high accuracy in classification tasks. This paves the way to develop the high energy-efficiency FeFET RC networks.