We have fabricated and demonstrated ultrathin In-Ga-Zn-O (IGZO) channel ferroelectric HfO2 field effect transistor (FET) with memory operation. Ultrathin-body IGZO ferroelectric FET (FeFET) shows high mobility and nearly ideal subthreshold slop with minimum 8 nm channel thickness, thanks to the properties of IGZO material, junctionless FET operation, nearly-zero low-k interfacial layer on metal-oxide channel and effective capping for realizing ferroelectric phase formation with HfZrO2 (HZO). The controllable memory operations are achieved with the use of back gate. The design guideline of IGZO FeFET is proposed by discussing the thickness of front gate oxide HZO and back gate oxide SiO2 using TCAD simulation. The material and electrical properties of metal/HZO/IGZO/metal capacitor are also investigated. Metal/HZO/IGZO/metal capacitor has up to 108 endurance and over one-year retention. IGZO FeFET shows a potential for high-density and low-power memory application.

We have developed and integrated a mobility-enhanced FET and a wakeup-free ferroelectric (FE) capacitor using Sn-doped InGaZnO (IGZTO) and demonstrated 1T1C FeRAM cell operation for 3-D embedded RAM application. IGZTO FET can achieve >20 cm ² /V $\cdot $ s mobility with an ultrathin channel, which is $2\times $ higher than InGaZnO (IGZO) FET. The physics of mobility enhancement in oxide semiconductor FET with IGZTO channel is investigated by both experimental and simulation methods. The FE capacitor with large remanent polarization and low-temperature process at 400 °C is achieved. We have also studied the impact of thin-film access transistors on 1T1C cell operation with gate voltage dependence and capacitor size dependence. SPICE simulation is used for an extremely scaled device that achieves ~ns operation. The proposed memory technology will enable high-density and energy-efficient computing by the proximity of processor core and memory in monolithic 3-D integration.

A metal/ferroelectric (FE)-HfO₂/IGZO/metal capacitor was fabricated and investigated for 3D high-density memory application. The sharp interface is obtained without atomic interdiffusion. The capacitor shows ferroelectricity with a IGZO capping layer. The endurance and retention measurement show that the capacitor has up to 10⁸ program/erase endurance cycles and a 10 year retention, respectively. The capacitor does not show the wake-up effect, which is beneficial for circuit design and manufacturing. The asymmetric imprint effect is attributed to the different band modulation in the accumulation and depletion states of IGZO.

We have monolithically integrated resistance random access memory (RRAM) array with oxide semiconductor channel access transistor in 3-D stack, achieved uniform memory characteristics of 1T1R cells at each layer, and demonstrated basic functionality of XNOR operation as in-memory computing for binary neural network (BNN) artificial intelligence (AI) applications. The integrated TiN/Ti/HfO ₂ /Ti stack RRAM shows high on/off ratio with stable retention and endurance properties. The indium gallium zinc oxide (IGZO) channel field-effect transistor (FET) works as an access transistor, which realized the low-temperature process, high mobility, and high drive current for RRAM. With the peripheral circuit, we demonstrate the XNOR operation using a pair of 1T1R cells. The impact of RRAM bit error rate on neural network is also investigated, which indicates the property of error-resilience in BNN. The 3-D neural network built by this architecture has high potential to enable area-efficient, low-power, and low-latency computing.

We have investigated the memory characteristics of InGaZnO (IGZO)-channel ferroelectric FETs (FeFETs) with 2D planar and 3D structures by TCAD simulation to improve the memory window (MW) with a floating-body channel for high-density memory applications. From the study on 2D planar FeFETs with a single gate and a double gate, the MW depends on channel length (L) and is enhanced with shorter L due to stronger electrostatic coupling from the source and drain to the center region of the IGZO layer. From the study on 3D structure FeFETs with macaroni (MAC) and nanowire (NW) structures, a large MW can be obtained especially in NW FeFETs due to the electric field concentration by Gauss’s law in the 3D electrostatics. Furthermore, we have systematically studied and discussed the device design of MAC and NW structure FeFETs in terms of the diameter and thickness for high-density memory applications. As the IGZO thickness and the outer diameter of the IGZO layer decrease, the MW increases due to the voltage divider and the electric field concentration. The device parameters that can maximize the MW can be determined under the constraints of the layout and material based on this study.

This study explores the impact of oxygen vacancy defects on elevated-metal metal-oxide (EMMO) IGZO TFTs under positive bias stress (PBS) using TCAD and DFT simulation. Findings reveal that oxygen vacancies accumulating at the channel/passivation layer interface and within the channel under PBS lead to negative threshold voltage shifts and reduced mobility. Additionally, higher tail state densities contribute to a positive Vth shift. These results provide important insights into the defect-related reliability of EMMO IGZO TFTs, guiding the design of more reliable devices.