In this letter, we demonstrate the competitive interaction between different row hammer (rh) leakage mechanisms in sub-20 nm DRAM and its implications for process optimization. Using 3D TCAD simulation, the leakage induced by electron migration (EM) and capacitive crosstalk (CC) can be separately analyzed, revealing their competitive role in WL etching depth (ED). When both mechanisms coexist, an optimal WL ED that most effectively suppresses the rh effect is observed. The optimal value, depending on the relative contribution of each leakage mechanism, varies with failure threshold and crosstalk noise voltage amplitude. The results highlight the importance of understanding and assessing the competitive interaction between different rh leakage mechanisms for effective rh mitigation.

In this article, we explored the underlying physical mechanisms of RowPress (RP)-induced leakage and its key features in sub-20 nm dynamic random access memory (DRAM). Employing 3-D TCAD simulations, single-sided and double-sided RP were studied and compared with their row hammer (RH) counterparts, focusing on the mechanisms of electron migration (EM) and capacitive crosstalk (CC). The results reveal that RP-induced leakage is not primarily driven by e-trap-assisted EM and CC mechanisms, which are the primary causes of the RH effect. Instead, it is the increased electrical field that facilitates EM, acting as the main contributor to the RP effect. Furthermore, the bit-flip directionality, temperature dependence, access pattern dependence, and data pattern dependence of RP were studied and differences from RH were emphasized, with the underlying mechanisms being thoroughly examined. The scalability of the RP effect is also evaluated. The findings provide a solid theoretical foundation for developing effective mitigation techniques and for the design of DRAM chips with enhanced reliability and security.

In this paper, the effect of TiN capping layer on interface quality and the channel hot carrier (CHC) reliability of high-k/metal-gate (HKMG) nMOSFET was investigated. Experiments show that the fresh interface trap density was reduced from 1.83×1011 cm-2 to 7.75×1010 cm-2 for 1.4nm and 2.4nm ALD TiN capping layers respectively, while the CHC time-to-failure was worsened by 13%. Combining the chemical analysis by secondary ion mass spectroscopy and the characterization of active energy for trap generation, it’s found that the extraordinary chlorine introduced by ALD TiN capping layer deposition could be responsible for the improved fresh interfacial trap but degraded CHC reliability in HKMG nMOSFETs. The mechanism can be explained by the lower binding energy of Si-Cl than Si-H, which results in more interface passivation but easier to be broken by electrical stress. This finding can provide the guide for the optimization of HKMG process.

In Part II of this article, we explore the effect of positive bias temperature instability (PBTI) aging on the retention time distribution. By combining TCAD simulations with experiments, we identified the spatial location and energy-level distribution of pre-existing and generated interface states. According to the defect-based compact leakage model established in Part I, simulations reveal the nonnegligible influence of PBTI aging effects on the retention time distribution. Additionally, the effects of buried-channel-array-transistors (BCATs) device parameters and random dopant fluctuation (RDF) on static leakage have been incorporated into the compact model, aiming to optimize the time-zero retention time of weak cells. Investigations focused on several key device parameters in the storage contact (SC) and wordline (WL) overlap region suggest that decreasing the work function (WF) of the top gate is a beneficial strategy. However, optimizing this key parameter will increase the degradation rate of the retention time of weak cells due to the PBTI-induced aging effect. Therefore, when designing aging-aware BCAT devices, tradeoffs need to be made between time-zero retention time, long-term retention time, and read/write performance.

In this study, ultra-fast methods were used to measure the threshold voltage shift (ΔV _T ) of the negative bias temperature instability (NBTI) in p-channel complementary metal oxide semiconductor field effect transistors (p-CMOSFETs) with a high-klmetal gate (HK/MG) stack. The voltage (Vg,str) and temperature (T) dependence of the NBTI time exponent (n) were studied under a wide range of stress conditions, and the results demonstrated a strong T dependence of n above room temperature (RT) and that the field reduction effect played an important role in determining the dependence of n on Vg,str and T. With the direct current current-voltage (DCIV) method, the similarity of n, activation energy (EA) and voltage acceleration factor (Γ) between the trap generation (ΔN _T ) and ΔV _T indicates that ΔN _T is the dominant subcomponent at higher values of T. The impact of the field reduction effect on the time exponents of ΔV _T and ΔV _T , E _A , and Γ were also investigated.