High performance negative capacitance (NC) p-type FinFETs (p-FinFETs) with a 3-nm-thick ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer are fabricated based on a conventional high-κ metal gate (HKMG) FinFETs fabrication flow. The devices show improved subthreshold swing (SS) values (34.5 mV/dec for 500-nm gate length (LG) and 53 mV/dec for 20-nm-LG devices) and slight hysteresis voltages (~9 mV for LG = 500 nm and ~40 mV for LG = 20 nm transistors). With the integrated FE film, a strong driving current enhancement (up to 260%) is also obtained compared with that of conventional FinFETs. The inherent reasons for the improved characteristics contribute to the low interface state density (Dit) and the perfect channel electrostatic integrity.

In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 10¹⁸ cm⁻³, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger I_ON/I_OFF ratio (3.15 × 10⁵) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed. The proposed sub-fin design demonstrates systematical technical advantages by calibrated 3D TCAD simulation, including 70% reduction in sub-channel gate-induced drain leakage (GIDL) current, over 20% promotion for on-off current ratio ( $\text{I}_{\mathrm{ on}}/\text{I}_{\mathrm{ off}}$ ) as well as improvement in sub-threshold slope (SS). The revealed narrow sub-fin offers nearly 10% on-state current promotion and gate controllability improvement for the NS-FETs with relatively lower ground-plane-concentration. The narrow sub-fin technique provides a new approach for suppressing PCE in the NS-FETs and indicates a promising supplementary technology adopted for the optimization of NS-FET fabrication process in sub-3nm technology node.

Acute kidney injury (AKI) is a frequently occurring severe disease with high mortality. Cystatin C (Cys-C), as a biomarker of early kidney failure, can be used to detect and prevent acute renal injury. In this paper, a biosensor based on a silicon nanowire field-effect transistor (SiNW FET) was studied for the quantitative detection of Cys-C. Based on the spacer image transfer (SIT) processes and channel doping optimization for higher sensitivity, a wafer-scale, highly controllable SiNW FET was designed and fabricated with a 13.5 nm SiNW. In order to improve the specificity, Cys-C antibodies were modified on the oxide layer of the SiNW surface by oxygen plasma treatment and silanization. Furthermore, a polydimethylsiloxane (PDMS) microchannel was involved in improving the effectiveness and stability of detection. The experimental results show that the SiNW FET sensors realize the lower limit of detection (LOD) of 0.25 ag/mL and have a good linear correlation in the range of Cys-C concentration from 1 ag/mL to 1 pg/mL, exhibiting its great potential in the future real-time application.

Complementary FET (CFET) is a promising booster for further area reductions in static random-access memory (SRAM) cells. However, the performance degrading by a series of parasitic parameters in these SRAM cells will diminish the scaling benefit introduced by new transistor architectures. In this article, we propose a universal methodology to determine the layout optimization direction of 6T static random-access memory (6T-SRAM) cells by studying the sensitivity of 6T-SRAM cell performance to various parasitic parameters. And adopt this method to optimize the CFET SRAM cell layout structure under the advanced nodes beyond 3 nm. The performances of CFET 6T-SRAM cells with different layout schemes are comparatively evaluated. It is found that the influence of the parasitic resistance on 6T-SRAM performances is double-sided, and parasitic resistances from transistor to power rail ( ${R}_{\mathrm {pds}}$ , ${R}_{\mathrm {pud}}$ ) and from access (AX) devices to bit-lines (BLs) ( ${R}_{\mathrm{bax}}$ ) have the most important effect on improving read noise margin (RNM) together with write margin (WM). The BL-first scheme with reduced ${R}_{\mathrm{bax}}$ and increased ${R}_{\mathrm {pud}}$ is proven to have 76.3% improvement in WM and 122.5% decrease in write time (WT) compared to the BL-last scheme, and a 63.8% improvement in RNM compared to conventional nanosheet architecture. Further optimized ${R}_{\mathrm{bax}}$ in the buried-BL scheme is proven to have higher WM, as well as lower WT. The BL-first scheme and buried-BL scheme is proven to be the most efficient approach to boost CFET SRAM performance.