Qingzhu Zhang

Dr. Qingzhu Zhang

Institute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, China;
orcid

Research Focus & Metrics

Academic Career Length

12Years (2015-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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30 April 2019 in Micromachines
Verified
Journal Article
Open access
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HRHenry Radamson
Henry Radamson
XHXiaobin He
Xiaobin He
Qingzhu ZhangQingzhu Zhang
Qingzhu Zhang
JLJinbiao liu
Jinbiao liu
HCHushan Cui
Hushan Cui
GWGuilei Wang
Guilei Wang
When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today’s 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

1 March 2019 in IEEE Electron Device Letters
Verified
Journal Article
Closed access
ZZZhaohao Zhang
Zhaohao Zhang
GXGaobo Xu
Gaobo Xu
Qingzhu ZhangQingzhu Zhang
Qingzhu Zhang
ZHZhaozhao Hou
Zhaozhao Hou
JLJunjie Li
Junjie Li
TYTianchun Ye
Tianchun Ye
High performance negative capacitance (NC) p-type FinFETs (p-FinFETs) with a 3-nm-thick ferroelectric (FE) hafnium zirconium oxides (Hf0.5Zr0.5O2) layer are fabricated based on a conventional high-κ metal gate (HKMG) FinFETs fabrication flow. The devices show improved subthreshold swing (SS) values (34.5 mV/dec for 500-nm gate length (LG) and 53 mV/dec for 20-nm-LG devices) and slight hysteresis voltages (~9 mV for LG = 500 nm and ~40 mV for LG = 20 nm transistors). With the integrated FE film, a strong driving current enhancement (up to 260%) is also obtained compared with that of conventional FinFETs. The inherent reasons for the improved characteristics contribute to the low interface state density (Dit) and the perfect channel electrostatic integrity.

30 May 2022 in Microsystems & Nanoengineering
Verified
Journal Article
Open access
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WZWenjie Zhao
Wenjie Zhao
JHJiawei Hu
Jiawei Hu
JLJinlong Liu
Jinlong Liu
XLXin Li
Xin Li
SSSheng Sun
Sheng Sun
Chengjun HuangChengjun Huang
Chengjun Huang
Exosomes are highly important in clinical diagnosis due to their high homology with their parental cells. However, conventional exosome detection methods still face the challenges of expensive equipment, low sensitivity, and complex procedures. Field effect transistors (FETs) are not only the most essential electronic component in the modern microelectronics industry but also show great potential for biomolecule detection owing to the advantages of rapid response, high sensitivity, and label-free detection. In this study, we proposed a Si nanowire field-effect transistor (Si-NW Bio-FET) device chemically modified with specific antibodies for the electrical and label-free detection of exosomes. The Si-NW FETs were fabricated by standard microelectronic processes with 45 nm width nanowires and packaged in a polydimethylsiloxane (PDMS) microfluidic channel. The nanowires were further modified with the specific CD63 antibody to form a Si-NW Bio-FET. The use of the developed Si-NW Bio-FET for the electrical and label-free detection of exosomes was successfully demonstrated with a limit of detection (LOD) of 2159 particles/mL. In contrast to other technologies, in this study, Si-NW Bio-FET provides a unique strategy for directly quantifying and real-time detecting exosomes without labeling, indicating its potential as a tool for the early diagnosis of cancer.

5 March 2021 in Nanomaterials
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Journal Article
Open access
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Qingzhu ZhangQingzhu Zhang
Qingzhu Zhang
Gu JieGu Jie
Gu Jie
RXRenren Xu
Renren Xu
Lei CaoLei Cao
Lei Cao
JLjunjie li
junjie li
JLJun Luo
Jun Luo
In this paper, the optimizations of vertically-stacked horizontal gate-all-around (GAA) Si nanosheet (NS) transistors on bulk Si substrate are systemically investigated. The release process of NS channels was firstly optimized to achieve uniform device structures. An over 100:1 selective wet-etch ratio of GeSi to Si layer was achieved for GeSi/Si stacks samples with different GeSi thickness (5 nm, 10 nm, and 20 nm) or annealing temperatures (≤900 °C). Furthermore, the influence of ground-plane (GP) doping in Si sub-fin region to improve electrical characteristics of devices was carefully investigated by experiment and simulations. The subthreshold characteristics of n-type devices were greatly improved with the increase of GP doping doses. However, the p-type devices initially were improved and then deteriorated with the increase of GP doping doses, and they demonstrated the best electrical characteristics with the GP doping concentrations of about 1 × 1018 cm−3, which was also confirmed by technical computer aided design (TCAD) simulation results. Finally, 4 stacked GAA Si NS channels with 6 nm in thickness and 30 nm in width were firstly fabricated on bulk substrate, and the performance of the stacked GAA Si NS devices achieved a larger ION/IOFF ratio (3.15 × 105) and smaller values of Subthreshold swings (SSs) (71.2 (N)/78.7 (P) mV/dec) and drain-induced barrier lowering (DIBLs) (9 (N)/22 (P) mV/V) by the optimization of suppression of parasitic channels and device’s structure.

23 July 2018 in IEEE Journal of the Electron Devices Society
Verified
Journal Article
Open access
JYJiaxin Yao
Jiaxin Yao
HYHuaxiang Yin
Huaxiang Yin
WWWenwu Wang
Wenwu Wang
JLJun Li
Jun Li
KLKun Luo
Kun Luo
ZWZhenhua Wu
Zhenhua Wu
We present a comprehensive theoretical investigation of the quantum confinement limited mobility in the Si1-xGex-channel gate-all-around (GAA) nanosheet field effect transistor (NSFET) for 5 nm node. The study encompasses physics-based quantum mechanical models both for P and NMOS with specified channel/wafer orientations and channel thicknesses, including (1) k.p model with Poisson solver for band structures, bandgap variations, and confined charge distributions, (2) Kubo-Greenwood model for low field mobility with considering surface roughness and stress, (3) Multi-subband Boltzmann transport equation (BTE) based on a state-of-the-art phase space approach is employed to evaluate device IV characteristics, (4) the threshold voltage (VT) variations with different channel/wafer orientations are also evaluated. Our simulation study shows that {110} wafer Ge channel can be an attractive option for 5nm node PMOS, and Si is still promising for NMOS due to strong quantum confinement in Ge channel.

19 February 2018 in IEEE Electron Device Letters
Verified
Journal Article
Closed access
Qingzhu ZhangQingzhu Zhang
Qingzhu Zhang
HYHuaxiang Yin
Huaxiang Yin
LMLingkuan Meng
Lingkuan Meng
JYJiaxin Yao
Jiaxin Yao
JLJunjie Li
Junjie Li
TYTianchun Ye
Tianchun Ye
In this letter, Gate-All-Around (GAA) nanowire (NW) p-MOSFETs with new approaches to fabricate totally isolated channels in replacement metal gate (RMG) are reported for the first time. Few reformed fin forming processes based on conventional high-k/metal gate FinFET flow are implemented to fabricate the GAA devices. Two profiles of NW channels, such as circular and inverted droplet, were fabricated by H2 baking and oxidation methods in the RMG process. The proposed methods would increase the process thermal budget and improve film quality for the NW channels. Providing both structural and process advantages, the optimized devices with Lg = 16 nm demonstrate superb short-channel effect (SCE) immunity characteristics, with SS = 61.86 mV/dec and DIBL = 6.5 mV/V for the inverted droplet NW device; these results are very close to the ideal limits of MOSFETs. The results also indicate that the inverted droplet NW devices have a slightly better SCE control than the circular NWs of similar geometric size.