This work is focused on the design and the experimental characterization of an analog channel developed for the read out of lithium-drifted silicon detectors of the General AntiParticle Spectrometer experiment aimed at the search for dark matter. The instrument is designed for the identification of antideuteron particles from cosmic rays during an Antarctic balloon mission scheduled for late 2022. A low-noise analog front-end, featuring a dynamic signal compression to comply with the wide input range, has been designed in a commercial 180 nm CMOS technology. The channel was fabricated in 2018 and is the first building block toward the development of a multichannel readout ASIC. The paper will provide a description of the design criteria, the architecture of the channel, and a summary of the results of the experimental characterization.

The linear front-end is the analog processor chosen for the final integration into the pixel readout chip for the high-luminosity upgrade of the CMS experiment at the large hadron collider. The front-end has been included in the RD53A chip, designed by the CERN RD53 collaboration and submitted in 2017. An optimized version of the front-end has been designed, submitted, and tested in the framework of the RD53B developments. The optimization is mainly concerned with the time-walk performance of the front-end and with its threshold tuning capabilities. The article describes in detail such design improvements together with the results from the characterization of a small prototype chip including a 16 $\times $ 16 pixel matrix featuring both the RD53A and RD53B versions of the front-end. Test results show a significant reduction, about 10 ns for input signals close to the threshold, of the time-walk in the RD53B front-end, featuring a threshold dispersion smaller than 65 electrons r.m.s. after exposure to a total ionizing dose of 1 Grad of X-rays.

This work describes the architecture and the experimental results from the characterization of a 32-channels mixed-signal Application-Specific Integrated Circuit (ASIC) developed for the readout of the lithium-drifted silicon, Si(Li), detectors of the General AntiParticle Spectrometer (GAPS) experiment dedicated to searching for dark matter. The instrument is designed for the identification of antiprotons, antideuterons and antihelium nuclei from cosmic rays during an Antarctic balloon mission scheduled for late 2024. A full custom integrated circuit, named SLIDER32 (32-channels Si-LI DEtector Readout) ASIC, has been produced in a commercial 180 nm CMOS technology. The ASIC is comprised of 32 low-noise analog readout channels featuring dynamic signal compression to comply with the wide input range, an 11-bit SAR ADC and a digital back-end section which is responsible for channel setting and for sending digital information to the data acquisition system (DAQ). The circuit design criteria and the experimental results are discussed in the paper.

A charge preamplifier has been developed in a 65-nm CMOS technology for processing the signals from the inner pixel layers of the CMS detector, in view of the experiment upgrade for the High-Luminosity (HL) Large Hadron Collider (LHC). The circuit is part of a readout channel implementing a time-over-threshold method for the analog-to-digital conversion of the input charge signal. Samples of the circuit have been exposed to high doses of ionizing radiation, up to 500 Mrad(SiO₂), from a low-energy proton source and from an X-ray tube. The test results show that the performance degradation, in terms of charge sensitivity, signal shape, and noise, is compatible with operation in the harsh environment of the HL-LHC. Measurement data from the characterization of preamplifiers using different kinds of capacitors in the feedback network help to gain some insight into the damage mechanisms in pMOS transistors irradiated with large ionizing doses. The dependence of performance degradation on the kind of radiation source used in the tests is also discussed.

This paper studies the effect of high levels of ionizing radiation on the analog parameters, with particular emphasis on the small signal and noise characteristics, of MOSFET devices belonging to a 28 nm bulk CMOS technology. The effects of total ionizing dose (TID) on drain leakage current, threshold voltage, transconductance, gate leakage current, intrinsic gain, and 1/f noise are studied. Post-irradiation annealing reverses the performance degradation of some analog parameters by neutralizing oxide-trapped charge. The results show the extreme radiation hardness of this technology node, proving its applicability in high energy physics experiments and photon science applications.

In the last few years, the 28 nm CMOS technology has raised interest in the High Energy Physics community for the design and implementation of readout integrated circuits for high granularity position sensitive detectors. This work is focused on the characterization of the 28 nm CMOS node with a particular focus on the analog performance. Small signal characteristics and the behavior of the white and 1/f noise components are studied as a function of the device polarity, dimensions, and bias conditions to provide guidelines for minimum noise design of front-end electronics. Comparison with data extracted from previous CMOS generations are also presented to assess the performance of the technology node under evaluation.