Roll-to-roll (R2R) printing methods are well known as additive, cost-effective, and ecologically friendly mass-production methods for processing functional materials and fabricating devices. However, implementing R2R printing to fabricate sophisticated devices is challenging because of the efficiency of material processing, the alignment, and the vulnerability of the polymeric substrate during printing. Therefore, this study proposes the fabrication process of a hybrid device to solve the problems. The device was created so that four layers, composed of polymer insulating layers and conductive circuit layers, are entirely screen-printed layer by layer onto a roll of polyethylene terephthalate (PET) film to produce the circuit. Registration control methods were presented to deal with the PET substrate during printing, and then solid-state components and sensors were assembled and soldered to the printed circuits of the completed devices. In this way, the quality of the devices could be ensured, and the devices could be massively used for specific purposes. Specifically, a hybrid device for personal environmental monitoring was fabricated in this study. The importance of environmental challenges to human welfare and sustainable development is growing. As a result, environmental monitoring is essential to protect public health and serve as a basis for policymaking. In addition to the fabrication of the monitoring devices, a whole monitoring system was also developed to collect and process the data. Here, the monitored data from the fabricated device were personally collected via a mobile phone and uploaded to a cloud server for additional processing. The information could then be utilized for local or global monitoring purposes, moving one step toward creating tools for big data analysis and forecasting. The successful deployment of this system could be a foundation for creating and developing systems for other prospective uses.

Integrating electronics into three-dimensional devices represents a significant advancement. There are two primary methods for manufacturing 3D electronic products: creating the curved product first and then applying printed electrodes by the non-contact printing method, or printing conductive patterns first on a film, followed by thermoforming. In this study, the latter method was chosen for its ease of manufacturing, cost-effectiveness, scalability, and ability to produce detailed patterns. The previous methods of manufacturing In-mold Electronics (IME) via thermoforming often introduce defects (cracks) that affect circuit conductivity. To fabricate a 3D IME-LED array, screen printing and thermoforming on a Polyethylene Terephthalate Glycol (PETG) substrate was utilized. For the reduction of conduction issues, a silver paste with a polyester resin (thermoplastic) binder was employed. Results demonstrated that the 3D IME circuit demonstrated elongation in length ranging from 5.9 to 6.7% before and after thermoforming, confirming its stretchability. Under optimal temperature of 110 °C and a vacuum level of – 3 psi, resistance decreased by 18%. Additionally, printed lines with a minimal width of 100 μm became conductive following this technique. This was achieved by taking advantage of the paste’s sintering and viscoelastic characteristics during the thermoforming process. This experiment demonstrates a novel approach to integrating electronics into 3D structures, providing valuable insights into the field of IME.

Recent advances in chiplet architectures, heterogeneous integration, 2.5D/3D packaging, high-performance computing, and RF applications have increased the demand for high-density vertical interconnects and low-loss packaging platforms. Glass substrates have attracted considerable attention for next-generation advanced packaging because of their low dielectric loss, high dimensional stability, smooth surface, and compatibility with large-area panel-level processing. Through-glass vias (TGVs) are essential vertical interconnect structures that enable the electrical integration of glass substrates. This focused review summarizes TGV technologies for glass-based advanced packaging from the perspectives of via formation, seed layer deposition, metallization, Cu filling, defect formation, reliability, and plugging-based alternative architectures. Representative TGV formation methods, including laser drilling, selective laser etching, laser-induced deep etching, wet/dry etching, and photosensitive glass processing, are compared. Metallization approaches based on sputtering, electroless plating, ALD/CVD, and hybrid processes are discussed together with Cu electroplating strategies such as conformal plating, bottom-up filling, pulse or pulse-reverse plating, and engineered-geometry filling. Key defects, including voids, seams, pinch-off, seed discontinuity, Cu/glass interfacial delamination, glass cracking, and Cu protrusion, are reviewed in relation to thermomechanical reliability. Finally, polymer/dielectric plugging, plugging/re-drilling, conductive paste plugging, and hybrid Cu/plugging structures are discussed as application-specific alternatives for balancing electrical performance, reliability, manufacturability, yield, and cost.

Advanced packaging requires high-density interconnects with sub-10 μm design rules; however, conventional processes involving laser drilling and plasma desmearing increase dielectric surface roughness and degrade signal performance. A nanosecond ultraviolet (ns-UV) laser microvia process using a sacrificial metal barrier layer (SMBL) was developed to enable sub-10 μm via formation while preserving dielectric surface integrity. A Cu SMBL was introduced to block debris redeposition during laser irradiation and shield the dielectric from ion bombardment during plasma processing. By optimizing laser power, shot count, and SMBL thickness, approximately 8 μm microvias were formed in 10 μm thick Ajinomoto Build-up Film (ABF). The Cu SMBL facilitated heat dissipation, reducing the heat-affected zone and limiting lateral widening at the via entrance, resulting in improved via geometry and higher taper. The dielectric surface roughness increased significantly (>80 nm) when no SMBL was used during processing, whereas it remained nearly constant with the SMBL (Ra: 6.36 → 6.43 nm), thereby reducing current scattering at high frequencies. Adhesion of 0.46 kgf/cm was maintained after quick-via-pull testing without mechanical interlocking, with no interfacial separation observed, confirming reliable interconnect formation. Therefore, the SMBL process enables precise microvia fabrication and low-loss interconnects for high-frequency packaging.