In this study, we investigated the brittle fracture behavior of Sn-3.0Ag-0.5Cu (SAC305) solder joints with a Direct Electroless Gold (DEG) surface finish, formed using laser-assisted bonding (LAB) and mass reflow (MR) techniques. Commercial SAC305 solder balls were used to ensure consistency. LAB increases void fractions and coarsens the primary β-Sn phase with higher laser power, resulting in a larger eutectic network area fraction. In contrast, MR produces solder joints with minimal voids and a thicker intermetallic compound (IMC) layer. LAB-formed joints exhibit higher high-speed shear strength and lower brittle fracture rates compared to MR. The key factor in the reduced brittle fracture in LAB joints is the thinner IMC layer at the joint interface. This study highlights the potential of LAB in enhancing the mechanical reliability of solder joints in advanced electronic packaging applications.

Recent advances in chiplet architectures, heterogeneous integration, 2.5D/3D packaging, high-performance computing, and RF applications have increased the demand for high-density vertical interconnects and low-loss packaging platforms. Glass substrates have attracted considerable attention for next-generation advanced packaging because of their low dielectric loss, high dimensional stability, smooth surface, and compatibility with large-area panel-level processing. Through-glass vias (TGVs) are essential vertical interconnect structures that enable the electrical integration of glass substrates. This focused review summarizes TGV technologies for glass-based advanced packaging from the perspectives of via formation, seed layer deposition, metallization, Cu filling, defect formation, reliability, and plugging-based alternative architectures. Representative TGV formation methods, including laser drilling, selective laser etching, laser-induced deep etching, wet/dry etching, and photosensitive glass processing, are compared. Metallization approaches based on sputtering, electroless plating, ALD/CVD, and hybrid processes are discussed together with Cu electroplating strategies such as conformal plating, bottom-up filling, pulse or pulse-reverse plating, and engineered-geometry filling. Key defects, including voids, seams, pinch-off, seed discontinuity, Cu/glass interfacial delamination, glass cracking, and Cu protrusion, are reviewed in relation to thermomechanical reliability. Finally, polymer/dielectric plugging, plugging/re-drilling, conductive paste plugging, and hybrid Cu/plugging structures are discussed as application-specific alternatives for balancing electrical performance, reliability, manufacturability, yield, and cost.

In this study, the effect of growth of intermetallic compound (IMC) layer between Au-20 wt% Sn solder and electroless Ni/immersion Au (ENIG) on the thermal resistance of a flip-chip (FC) light emitting diode (LED) package was investigated. Two IMC layers were formed at the interface of FC LED package, including Au ₅ Sn and (Ni, Au) ₃ Sn ₄ that were identified using a transmission electron microscopy. A thermal aging test was carried out at 200 °C for 1000 h to observe IMCs growth. After 1000 h, the (Ni, Au) ₃ Sn ₄ thickness increased to about 1.5 μ m and the thermal resistance of the FC LED package increased by 3.5 times compared to the initial thermal resistance of 2 K W ⁻¹ . As the (Ni, Au) ₃ Sn ₄ grew, a calculation of thermal resistance also increased comparing to the initial aging test, thus, the growth of (Ni, Au) ₃ Sn ₄ layer can be effective factor on the increase of thermal resistances of FC LED package.

Advanced packaging requires high-density interconnects with sub-10 μm design rules; however, conventional processes involving laser drilling and plasma desmearing increase dielectric surface roughness and degrade signal performance. A nanosecond ultraviolet (ns-UV) laser microvia process using a sacrificial metal barrier layer (SMBL) was developed to enable sub-10 μm via formation while preserving dielectric surface integrity. A Cu SMBL was introduced to block debris redeposition during laser irradiation and shield the dielectric from ion bombardment during plasma processing. By optimizing laser power, shot count, and SMBL thickness, approximately 8 μm microvias were formed in 10 μm thick Ajinomoto Build-up Film (ABF). The Cu SMBL facilitated heat dissipation, reducing the heat-affected zone and limiting lateral widening at the via entrance, resulting in improved via geometry and higher taper. The dielectric surface roughness increased significantly (>80 nm) when no SMBL was used during processing, whereas it remained nearly constant with the SMBL (Ra: 6.36 → 6.43 nm), thereby reducing current scattering at high frequencies. Adhesion of 0.46 kgf/cm was maintained after quick-via-pull testing without mechanical interlocking, with no interfacial separation observed, confirming reliable interconnect formation. Therefore, the SMBL process enables precise microvia fabrication and low-loss interconnects for high-frequency packaging.