Several Silicon on Insulator (SOI) wafer manufacturers are now offering products with customer-defined cavities etched in the handle wafer, which significantly simplifies the fabrication of MEMS devices such as pressure sensors. This paper presents a novel cavity buried oxide (BOX) SOI substrate (cavity-BOX) that contains a patterned BOX layer. The patterned BOX can form a buried microchannels network, or serve as a stop layer and a buried hard-etch mask, to accurately pattern the device layer while etching it from the backside of the wafer using the cleanroom microfabrication compatible tools and methods. The use of the cavity-BOX as a buried hard-etch mask is demonstrated by applying it for the fabrication of a deep brain stimulation (DBS) demonstrator. The demonstrator consists of a large flexible area and precisely defined 80 µm-thick silicon islands wrapped into a 1.4 mm diameter cylinder. With cavity-BOX, the process of thinning and separating the silicon islands was largely simplified and became more robust. This test case illustrates how cavity-BOX wafers can advance the fabrication of various MEMS devices, especially those with complex geometry and added functionality, by enabling more design freedom and easing the optimization of the fabrication process.

This paper presents a new method for the CMOS compatible fabrication of microchannels integrated into a silicon substrate. In a single-step DRIE process (Deep Reactive Ion Etching) a network of microchannels with High Aspect Ratio (HAR) up to 10, can be etched in a silicon substrate through a mesh mask. In the same single etching step, multidimensional microchannels with various dimensions (width, length, and depth) can be obtained by tuning the process and design parameters. These fully embedded structures enable further wafer processing and integration of electronic components like sensors and actuators in wafers with microchannels.

We present a novel, wafer-based fabrication process that enables integration and assembly of electronic components, such as ASICs and decoupling capacitors, with flexible interconnects. The electronic components are fabricated in, or placed on precisely defined and closely-spaced silicon islands that are connected by interconnects embedded in parylene-based flexible thin film. This fully CMOS compatible approach uses optimized DRIE processes and an SiO₂ mesh-shaped mask, allowing for the simultaneous definition of micrometer- to millimeter-sized structures without compromising the flexibility of the device. In a single fabrication flow a unique freedom in dimensions of both the flexible film and the silicon islands can be achieved making this new technique ideal for the realization of semi-flexible/foldable implantable devices, where structures of different sizes have to be combined together for the ultimate miniaturization.