The role of the magnesium (Mg) doping and its electrical activation on the off-state of p-GaN/AlGaN/GaN HEMTs has been investigated in this work. Firstly, the effect of different Mg doping profiles has been studied via the help of Technology Computer-Aided Design (TCAD) simulations, with the objective of analyzing the band diagrams of the structure. Then, it has been shown how experimental Capacitance–Voltage measurements can be useful to obtain information on the net acceptor concentration in the p-GaN. As a result, devices with an undoped (magnesium-free) GaN gate have been experimentally compared to devices whose p-GaN gate has been activated via a reference annealing process. Finally, results on a device characterized by an improved p-GaN activation have been presented and compared, showing improvements on several parameters of both off- and on-state, thus underlining the key role of the Mg activation process in the overall performances of normally-off GaN HEMTs.

In this paper, a new method for evaluating hot-electron degradation in p-GaN gate AlGaN/GaN power HEMTs is proposed. The method exploits a commercial parameter analyzer to study V_TH and R_ON drifts induced by on-state stress at V_DS = 50 V. The results show that V_TH drift and part of the R_ON degradation induced by the on-state stress are recoverable and likely due to the ionization of C-related acceptors in the buffer. This was confirmed by a preliminary characterization of C-related buffer traps. Conversely, the remaining part of R_ON degradation (not recovered in 1000 s) was strongly affected by the surface treatment. The current level set during on-state stress affected the amount of non-recoverable degradation, confirming the involvement of hot electrons. Thanks to the monitoring of the parameters’ recovery, the proposed method provides important insights into the physical mechanisms governing the parameters’ degradation. This extends the capabilities of state-of-the art systems, without the need for custom setup development.

In this paper, preliminary gate reliability of p-GaN HEMTs under high positive gate bias is studied. Gate robustness is of great interest both from an academic and industrial point of view; in fact, different tests and models can be explored to estimate the device lifetime, which must meet some minimum product requirements, as specified by international standards (AEC Q101, JESD47, etc.). However, reliability characterizations are usually time-consuming and are performed in parallel on multiple packaged devices. Therefore, it would be useful to have a faster method to screen out weaker gate trials, already on-wafer, before reaching the packaging step. For this purpose, a room-temperature stress procedure is presented and described in detail. Then, this screening test is applied to devices with a reference gate process, and, as a result, high gate leakage degradation is observed. Afterwards, a different process implementing a dielectric layer between p-GaN and gate metal is evaluated, highlighting the improved behavior during the stress test. However, it is also observed that devices with this process suffer from very high drain leakage, and this effect is then studied and understood through TCAD (technology computer-aided design) simulations. Finally, the effect of a surface treatment performed on the p-GaN is analyzed, showing improved gate pre-reliability while maintaining low drain leakage.

In this work, a novel understanding of the main failure mechanism of a Schottky p-GaN gate AlGaN/GaN HEMT subject to forward gate stress is reported. First an experimental characterization of the gate leakage current (I_GSS) at different temperatures is reported. Then, Technology Computer Aided Design (TCAD) simulations are used to reproduce the experimental I_GSS thanks to the impact ionization model, also at different temperatures. Simulation results underline how the stressed regions for the Device Under Test (DUT) at high gate biases are the Schottky/p-GaN interface, the p-GaN/AlGaN barrier interface, and p-GaN sidewalls. Moreover, Time Dependent Gate Breakdown (TDGB) measurements were done, and the TEM analysis on the failed device showed the lattice crystal damage located at the p-GaN/AlGaN interface, in accordance with TCAD simulations’ current density distribution at high voltage gate stress.

In this article modeling of back-biasing effects in Gallium Nitride (GaN) bidirectional high-electron-mobility transistors (HEMTs) is discussed. Specifically, static degradation of both on-resistance and threshold voltage due to negative substrate bias is considered. The study is carried out by adopting a bidirectional switch (BDS) model based on the well-known Advanced SPICE Model (ASM) for GaN HEMT. The back-biasing description natively included in the ASM code is analyzed, and then a novel formulation of the phenomenon is proposed. Both modeling approaches are extensively compared with DC and pulsed IV measurements, performed on wafer level and packaged devices in a monolithic 650 V normally off GaN on Silicon technology. The analyses carried out show that the proposed back-biasing model allows us to predict more accurately the experimental data at higher substrate voltages (i.e., beyond 150 V) compared to the reference one. Furthermore, some remarkable considerations concerning the performance degradation in the switching test with different substrate connections are reported.