This paper presents an extensive comparison of two 28-nm CMOS technologies, i.e., standard and mm-wave-optimized (i.e., thick metals and intermetal oxides) back-end-of-line (BEOL). The proposed comparison is carried out at both component and circuit level by means of a quantitative analysis of the actual performance improvements due to the adoption of a mm-wave-optimized BEOL. To this end, stand-alone transformer performance is first evaluated and then a complete mm-wave macroblock is investigated. A 77-GHz down-converter for frequency modulated continuous wave (FMCW) long-range/medium range (LR/MR) radar applications is exploited as a testbench. For the first time, it is demonstrated that thicker metals and intermetal oxides do not guarantee significant improvements at mm-wave frequencies and a standard (low-cost) BEOL is competitive in comparison with more complex (expensive) ones.

This paper presents the design of on-chip micro-antennas for package-scale galvanic isolators based on RF planar coupling. A step-by-step design procedure is proposed, which aims at the maximization of the weak electromagnetic coupling between the RX and TX antennas integrated on side-by-side co-packaged chips to enable both high isolation rating and common-mode transient immunity thanks to the high dielectric strength and low capacitive parasitics of a molding compound-based galvanic barrier, respectively. Micro-antenna design guidelines are drawn, highlighting the main relationship between coil coupling performance and their layout parameters, which are often in contrast with respect to traditional integrated inductor ones.

This brief presents a novel class-D oscillator topology conceived for galvanically isolated data transfer based on RF planar coupling. In its general implementation, it consists of n capacitively coupled stacked class-D oscillators, each one loaded by a primary transformer winding. Capacitive coupling between the oscillators guarantees robust frequency/phase synchronization. The oscillation voltages are combined at the secondary transformer winding, thus ideally producing the same oscillation amplitude of a class-D topology with a power consumption reduced by a factor of 1/n thanks to the current-reuse configuration. With respect to traditional topologies, capacitive-coupled stacked class-D oscillators also allow standard MOS transistors (i.e., with a low breakdown voltage) to be reliably operated at higher supply voltages. The oscillator advantages have been highlighted in comparison with the traditionally adopted complementary cross-coupled topology within an isolated data link based on RF planar coupling in a 0.18- $\mu \text{m}$ CMOS technology.

This paper presents a lumped scalable model for spiral inductors in a radio frequency (RF) gallium nitride (GaN) technology on silicon substrate. The model has been developed by exploiting electromagnetic (EM) simulations of geometrically scaled spiral inductors. To this aim, the technology substrate, i.e., the metal back-end-of-line along with dielectric and semiconductor layers of the adopted GaN process, has been validated by means of experimental data and then used to define the EM simulator set-up for the spiral inductors. The proposed model adopts a simple π-topology with only seven lumped components and predicts inductor performance in terms of inductance, quality factor (Q-factor) and self-resonance frequency (SRF) for a large range of geometrical parameters of the spiral (i.e., number of turns, metal width, inner diameter).

In this article modeling of back-biasing effects in Gallium Nitride (GaN) bidirectional high-electron-mobility transistors (HEMTs) is discussed. Specifically, static degradation of both on-resistance and threshold voltage due to negative substrate bias is considered. The study is carried out by adopting a bidirectional switch (BDS) model based on the well-known Advanced SPICE Model (ASM) for GaN HEMT. The back-biasing description natively included in the ASM code is analyzed, and then a novel formulation of the phenomenon is proposed. Both modeling approaches are extensively compared with DC and pulsed IV measurements, performed on wafer level and packaged devices in a monolithic 650 V normally off GaN on Silicon technology. The analyses carried out show that the proposed back-biasing model allows us to predict more accurately the experimental data at higher substrate voltages (i.e., beyond 150 V) compared to the reference one. Furthermore, some remarkable considerations concerning the performance degradation in the switching test with different substrate connections are reported.