In this paper, a new method for evaluating hot-electron degradation in p-GaN gate AlGaN/GaN power HEMTs is proposed. The method exploits a commercial parameter analyzer to study V_TH and R_ON drifts induced by on-state stress at V_DS = 50 V. The results show that V_TH drift and part of the R_ON degradation induced by the on-state stress are recoverable and likely due to the ionization of C-related acceptors in the buffer. This was confirmed by a preliminary characterization of C-related buffer traps. Conversely, the remaining part of R_ON degradation (not recovered in 1000 s) was strongly affected by the surface treatment. The current level set during on-state stress affected the amount of non-recoverable degradation, confirming the involvement of hot electrons. Thanks to the monitoring of the parameters’ recovery, the proposed method provides important insights into the physical mechanisms governing the parameters’ degradation. This extends the capabilities of state-of-the art systems, without the need for custom setup development.

In this paper, preliminary gate reliability of p-GaN HEMTs under high positive gate bias is studied. Gate robustness is of great interest both from an academic and industrial point of view; in fact, different tests and models can be explored to estimate the device lifetime, which must meet some minimum product requirements, as specified by international standards (AEC Q101, JESD47, etc.). However, reliability characterizations are usually time-consuming and are performed in parallel on multiple packaged devices. Therefore, it would be useful to have a faster method to screen out weaker gate trials, already on-wafer, before reaching the packaging step. For this purpose, a room-temperature stress procedure is presented and described in detail. Then, this screening test is applied to devices with a reference gate process, and, as a result, high gate leakage degradation is observed. Afterwards, a different process implementing a dielectric layer between p-GaN and gate metal is evaluated, highlighting the improved behavior during the stress test. However, it is also observed that devices with this process suffer from very high drain leakage, and this effect is then studied and understood through TCAD (technology computer-aided design) simulations. Finally, the effect of a surface treatment performed on the p-GaN is analyzed, showing improved gate pre-reliability while maintaining low drain leakage.

In this work, a novel understanding of the main failure mechanism of a Schottky p-GaN gate AlGaN/GaN HEMT subject to forward gate stress is reported. First an experimental characterization of the gate leakage current (I_GSS) at different temperatures is reported. Then, Technology Computer Aided Design (TCAD) simulations are used to reproduce the experimental I_GSS thanks to the impact ionization model, also at different temperatures. Simulation results underline how the stressed regions for the Device Under Test (DUT) at high gate biases are the Schottky/p-GaN interface, the p-GaN/AlGaN barrier interface, and p-GaN sidewalls. Moreover, Time Dependent Gate Breakdown (TDGB) measurements were done, and the TEM analysis on the failed device showed the lattice crystal damage located at the p-GaN/AlGaN interface, in accordance with TCAD simulations’ current density distribution at high voltage gate stress.

In this paper, the impact of SiN passivation on dynamic-R_ON degradation of AlGaN/GaN HEMTs devices is put in evidence. To this end, samples showing different SiN passivation stoichiometry are considered, labeled as Sample A and Sample B. For dynamic-R_ON tests, two different experimental setups are employed to investigate the R_ON-drift showing up during conventional switch mode operation by driving the DUTs under both (i) resistive load and (ii) soft-switching trajectory. This allows to discern the impact of hot carriers and off-state drain voltage stress on the R_ON parameter drift. Measurements performed with both switching loci shows similar dynamic-R_ON response, indicating that hot carriers are not involved in the degradation of tested devices. Nevertheless, a significant difference was observed between Sample A and Sample B, with the former showing an additional R_ON-degradation mechanism, not present on the latter. This additional drift is totally ascribed to the SiN passivation layer and is confirmed by the different leakage current measured across the two SiN types. The mechanism is explained by the injection of negative charges from the Source Field-Plate towards the AlGaN surface that are captured by surface/dielectric states and partially depletes the 2DEG underneath.

This paper presents the electrical characterization of the on-resistance (R_ON) of on-wafer 100 V p-GaN power High-Electron-Mobility Transistors (HEMTs). This study assesses device degradation in the context of a monolithically integrated half-bridge circuit, considering both Low-Side (LS) and High-Side (HS) configurations. Since on-wafer samples have been characterized, a custom experimental setup was developed to emulate stress conditions experienced by the devices in the half-bridge circuit. A periodic signal (T = 10 µs, T_ON = 2 µs) switching from the OFF to the ON state was applied for a cumulative duration of 1000 s. Different OFF-state stress conditions were applied by varying the gate-source OFF voltage (V_GS,OFF) between 0 V and −10 V. The on-resistance exhibited a positive drift over time for devices in either the LS or the HS configuration, with the latter showing a more pronounced degradation. Measurements at higher temperatures (up to 90 °C) were carried out to characterize the dynamics of the physical mechanism behind the degradation effects. We identified hole emission from C-related acceptor traps in the buffer as the main mechanism for the observed degradation, which is present in both the HS and the LS configurations. The additional degradation observed in the HS case was attributed to the back-gating effect, stemming from the non-null body-to-source voltage. Furthermore, we found that a more negative V_GS,OFF further increases R_ON degradation, likely related to the higher electric field near the gate contact, which enhances hole emission from C-related acceptor traps.

In this paper, four passive terminations are considered for the substrate biasing of Gallium Nitride (GaN) bidirectional high-electron-mobility transistors (HEMTs). These substrate networks are analyzed via switching simulations and by adopting a physical model for the bidirectional transistor based on the well-known Advanced SPICE Model (ASM) for GaN HEMT, including an enhanced formulation of back-gating phenomena. The most promising network, which exploits resistances and diodes in the common anode configuration, was implemented with discrete components and tested. The measurement data turned out to be in line with the simulations results in terms of substrate voltage, which is pushed toward zero at low resistance values, thus reducing the back-gating effect. Consequently, a remarkable reduction in the on-resistance (R_ON) degradation compared to the floating substrate configuration is observed, with a proper trade-off between R_ON drift and off-state leakage current. Finally, some considerations about the partial recovery of on-resistance due to the substrate termination are discussed.