State-of-the-art silicon carbide (SiC) power devices provide superior performance over silicon devices with much higher switching frequencies/speed and lower losses. High switching speed is preferred for achieving low switching loss, yet high dv/dt and di/dt can result in high EMI emission during switching transients. These switching dynamics can be controlled by the device gate driving strategy. The multi-level active gate driver (AGD) approach is able to tradeoff the switching losses with the dv/dt and di/dt for each switching transient. A novel three-level (3-L) AGD for SiC power mosfet trajectory control is introduced. Its turn-off profile has a shorter turn-off delay compared to any existing methodology. Accordingly, a comprehensive datasheet-driven trajectory model for the online model-based optimization of the 3-L turn-off is introduced. The main factors that impact the 3-L turn-off performance are analyzed with this model. The experimental results of double pulse tests validate the approach. Additionally, the benefits of the proposed 3-L AGD method over two-stage turn-off and conventional gate drivers on the market are illustrated through experiments.

The paper presents a simulation model of silicon carbide (SiC) power MOSFET that accurately predicts both the static and dynamic third quadrant behavior without compromising the first quadrant's accuracy. Unlike existing models, this model features an asymmetric third quadrant behavior for MOSFET characteristics necessary for accurate synchronous rectifier simulations. Moreover, it includes the gate-dependent body diode behavior, essential for accurate prediction of freewheeling high side device behavior in half-bridge configurations with significant gate voltage oscillation. The model also includes reverse recovery characteristics for accurate overshoot and power loss prediction. Despite having these added features, the model demonstrates good convergence and efficiency due to the replacement of conditional piecewise equations with continuous ones consisting of weighted variables. The model's convergence capability and efficiency have been verified by simulating a 5-level cascaded H-bridge multi-level inverter. The model's superior efficiency and accuracy have been validated by comparing it with an established SiC power MOSFET model. Also, an easy-to-follow parameter extraction procedure is documented that only requires data commonly available in commercial datasheets for broader utility. Considering accuracy, efficiency, and convenience, the model is useful for all power electronics converter applications

Gallium nitride (GaN) high electron mobility transistors (HEMTs) are excellent power semiconductor devices due to their superior material properties compared to their silicon (Si) counterparts. It has demonstrated a fast switching speed with high dV/dt, enabling the designer to push the switching frequency toward the MHz range. However, traditional wire-bonded packaging becomes a limiting factor in fully harnessing the benefits offered by these advanced power devices, as it is likely to introduce voltage overshoot, oscillation, parasitic turn-on, and electromagnetic interference (EMI) issues; thus, improved and advanced packaging structures are a must to bridge the gap. Besides, the unique electrical behavior and footprint of GaN compared to Si and Si carbide make them have different requirements for power module integration. To seek a viable solution, a globally optimized double-sided cooled, gate driver integrated 650-V/60-A GaN half-bridge power module is presented herein. The proposed 3-D integrated hybrid solution delivers an optimized package, having power loop inductance and thermal resistance as low as 0.91 nH and $0.38~^{\circ }\text{C}$ /W, respectively, which is verified using simulation and experimental results. The overall utility of the design improved proportionately by introducing simple, yet effective electrical/thermal codesign approaches, which can be applied to future power modules, designed for separate applications.

This paper presents a unified physics-based Insulated-Gate Bipolar Transistor (IGBT) compact model which predicts the performance of both Si and SiC, n- and p-channel devices. The model can predict the detailed switching waveforms of these technologies based on its charge-based formulation. Further, this novel IGBT compact model is presented alongside a unique datasheet-driven parameter extraction process. The parameter extraction process enables users to quickly extract model parameters from data typically published without the need of taking physical measurements. The model has been validated with both Si and SiC devices for static and dynamic characteristics. The SiC IGBTs used for validation are a 12.5 kV n-channel device and a 13 kV p-channel device, while the Si IGBT chosen was IXBK55N300 from IXYS. This is the only IGBT model that predicts the performance of both n- and p-channel, Si and SiC devices, providing more freedom for the development of complex power electronics circuit designs. The convergence of the model has been verified by implementing a complex circuit consisting of both a DC-DC converter and a DC-AC inverter. The results presented here show that the unified model can be used to describe the behavior of a wide range of Si and SiC IGBT circuits. This paper is accompanied by a Verilog-A source code and a power point file demonstrating the model parameter extraction sequence.

This paper presents an efficient physics-based electro-thermal model that solves some advanced problems of modeling Silicon Carbide (SiC) power MOSFETs. It is the first electro-thermal model that simulates the temperature dependency of the first and the third quadrant characteristics, including the reverse recovery of the body diode accurately and efficiently. It extends from a previous work that demonstrated the isothermal physics-based model of the gate-dependent body diode. Physics-based temperature scaling of the first and third quadrant allows simulation of the self-heating effect in a wide range of temperatures (27°C – 200°C), even for the synchronous operation. Moreover, a physics-based modeling approach is taken to include gate-voltage dependent non-linearity of the gate to source capacitance (Cgs). Also, a physic-based segmented cascaded method is taken to accurately model the Miller (Crss), and the output (Coss) capacitances at the low and very high drain to source voltage regions. Further, the temperature-dependent breakdown mechanism is included for reliable system design. Double Pulse Tests (DPTs) at various temperatures up to 200°C validate the model's accuracy. Lastly, a synchronous buck converter test demonstrates the model's ability to predict junction temperatures, validating the model's accuracy and efficiency in a continuous operation with self-heating.

This paper presents the SPICE model development of the static characteristics of SiC lateral n-channel and p-channel MOSFETs based on the widely used BSIM4 compact model. The methodology for length and width scaling of the MOSFETs is demonstrated. The transfer (ID – VG) and output (ID - VD) characteristics of the SiC low voltage MOSFETs are significantly different from their Si counterparts mainly due to the presence of the interface trapped charge, and proper modifications of the DC equations are required to accurately model the characteristics. The relatively poorer quality of the oxide-semiconductor interface in a SiC MOSFET compared to Si gives rise to valid energy states inside the bandgap. The trapped charges in these interface states are responsible for mobility degradation, higher subthreshold slope, soft saturation, increase in flat band and threshold voltage and exaggerated body effects. In this paper, the effects of the interface trapped charge on the static characteristics of the SiC MOSFETs are intensively studied and accurate compact models are developed and incorporated in the core BSIM4 DC current equations to accurately model the SiC MOSFET I-V behavior. A new parameter extraction sequence is also proposed to optimize the model and the simulated characteristics are matched with the measured characteristics of SiC MOSFET devices.