In this study, two new structures of single‐phase hybrid multilevel inverter are proposed for both symmetrical and asymmetrical configurations that can be employed in drives and control of electrical machines and connection of renewable energy sources. The proposed configuration uses a less number of semiconductor devices and DC sources as compared with conventional and newly developed topologies which lead to a reduction in cost and installation area. The proposed topology poses a vital advantage of self‐voltage balancing of its capacitor voltage regardless of load type, load dynamics and modulation index. Also, the proposed topology is expanded in a cascaded fashion which reduces the complexity and improves the performance significantly. A wide range of comparison is done with conventional and newly developed topologies to show the superior performance of proposed topologies regarding a total number of switches and DC sources. The multi‐carrier pulse‐width modulation strategy is adopted for generating switching pulses for respective switches. A laboratory prototype is developed for testing the performance of the proposed topology for 9‐level and 17‐level inverters.

This paper presents a single-phase symmetrical and asymmetrical multilevel inverter (MLI) topology. The presented topology can generate 9-level output voltage in a symmetrical configuration, 13-level and 17-level in asymmetrical configuration with a single cell. The number of output levels can be improved further by increasing either the number of cells or switches in a single cell. The presented topology contains the least number of DC sources, semiconductor switches, capacitors and diodes as compared to classical and recently proposed topologies. Reduction in component count decreases the size, complexity and cost of the overall converter. A detailed comparison has been done of the presented topology with recently proposed topologies in terms of DC sources, semiconductor switches, capacitor and total blocking voltage. Finally, to validate the presented concept, the prototype of the presented nine-level. Thirteen-level and seventeen-level MLI topologies have been tested in the laboratory for different switching frequencies, different modulation indexes, sudden load changes and nonlinear load.

Multilevel inverters (MLIs) have developed deep roots in various industrial sectors owing to their advantages over conventional two‐level inverters. However, the reliability of the semiconductor devices has been one of the major concerns for the proper functioning of MLI. Therefore, a novel fault‐tolerant topology is proposed in this study. The proposed topology is capable to tolerate single‐ and multi‐switch faults. It has lesser device count compared with the most recent work in the field. Moreover, it achieves inherent voltage balancing across capacitors. The proposed fault‐tolerant topology is simulated in MATLAB/Simulink and validated experimentally.

Reduced voltage stress and low‐total harmonic distortion are the main causes for such widespread application of multilevel inverters (MLIs) in various industrial sectors. However, reliability is one of the major concerns of MLIs as it uses a large number of switches as compared with two‐level inverters. Therefore, a newly developed transistor clamped H‐bridge inverter is proposed in the literature which uses a relatively less number of switches and DC sources as compared with cascaded H‐bridge but lacks in reliability due to the absence of redundant states. Hence, in this study, the reliability improvement strategy for newly developed five‐level transistor clamped H‐bridge‐based cascaded inverter is proposed which can be generalised for any number of levels. In the proposed fault tolerant strategy, the fault can be broadly classified based on the two main legs of the proposed inverter. Moreover, the proposed fault tolerant strategy does not require any kind of external circuit for maintaining its capacitor voltage in the balanced state. Finally, to validate the concept, a laboratory prototype of the five‐level inverter is developed and results are obtained successfully.

High failure rate of the semiconductor devices and capacitors, matched with their high requirement in the architecture of a multilevel inverter topology, results in low reliability of the inverter. A low device count, preserving the output power upon fault occurrence, ability to tolerate both open and short switch failure on all fault locations, handling both single and multiple switch failure, and achieving natural voltage balancing of the capacitors are the main challenges for the existing solutions to the fault tolerant topologies. Thus, a highly resilient fault tolerant topology, based on conventional inverters, is proposed in this paper. The proposed solution accomplishes all the challenges above without deteriorating the efficiency of the inverter during faulty conditions. The robustness and the effectiveness of the proposed topology are verified by the obtained experimental results. Multiple cases of switch failure are considered to cover all fault locations and types. Comparative analysis with the recently proposed fault-tolerant topologies on MLIs shows the superiority of the proposed topology over the rest.