This paper presents a single-phase symmetrical and asymmetrical multilevel inverter (MLI) topology. The presented topology can generate 9-level output voltage in a symmetrical configuration, 13-level and 17-level in asymmetrical configuration with a single cell. The number of output levels can be improved further by increasing either the number of cells or switches in a single cell. The presented topology contains the least number of DC sources, semiconductor switches, capacitors and diodes as compared to classical and recently proposed topologies. Reduction in component count decreases the size, complexity and cost of the overall converter. A detailed comparison has been done of the presented topology with recently proposed topologies in terms of DC sources, semiconductor switches, capacitor and total blocking voltage. Finally, to validate the presented concept, the prototype of the presented nine-level. Thirteen-level and seventeen-level MLI topologies have been tested in the laboratory for different switching frequencies, different modulation indexes, sudden load changes and nonlinear load.

Low reliability is one of the significant worries of multilevel inverter (MLI) and which results due to the presence of higher number of switches and capacitors as compared to the conventional two-level inverter. Consequently, Fault-tolerant (FT) operation of MLI has attracted significant research attention. Therefore, in this paper, a nine-level inverter topology with FT characteristics is discussed. The proposed topology is capable of tolerating short circuit (SC) and open circuit (OC) faults not only in the single switch but also in multiple switches. It preserves output power, voltage levels and capacitor voltage balancing under pre and post fault operation. The proposed MLI topology requires least number of DC sources, capacitors, switches, clamping diodes and total blocking voltage in comparison to recently proposed topologies. Thus, offering better efficiency profile under pre and post fault conditions. The proposed work has been validated experimentally with a laboratory prototype.

Multilevel inverters (MLIs) are widely employed in high power and high voltage applications due to their advantages like better power quality and lower voltage stress across power switches compared to the traditional two-level inverter. However, the utilization of higher number of power semiconductor devices and capacitors results in less reliability. In this regard, a fault-tolerant MLI (FTMLI) with asymmetrical source configuration is developed which can tolerate the open-circuit and short-circuit switch failures (single and multiple switch faults). The proposed topology preserves the output power and balances the capacitor's voltage under pre and postfault conditions. Further, a new switching scheme is proposed to reduce the ripple content in the capacitor's voltage. Further, under postfault operation uses less number of conducting switches resulting in a better efficiency. The proposed FTMLI generates a higher number of voltage levels with less number of component counts when compared with recently proposed topologies. Moreover, this comparative study reveals the prevalence of the proposed converter in the recent literature. The conducted experimental test proves the effectiveness and fault-tolerant feature of the proposed topology.

Reliability is one of the significant worries of multilevel inverter (MLI) owing to the higher number of capacitors and switches. In this regard, fault‐tolerant single‐phase MLI topology with improved reliability is proposed in this work. Apart from the reduced device count, the proposed topology has fault‐tolerant characteristics without any extra switches or legs. Moreover, the voltage of the capacitor is balanced under pre and post‐fault operation without any external circuit. Less number of the turn‐on devices and power losses promise higher reliability of the proposed topology in comparison with recently proposed topologies. The reliability of the proposed topology, as well as recently proposed topologies, has been evaluated. A detailed quantitative comparison of the proposed inverter topology has been carried out with the recent literature. The robustness and effectiveness of the proposed topology are carried out under various operating conditions in the SIMULINK environment. Finally, an experimental test bench of the proposed topology is built and the obtained experimental results validate the simulation results.

A low device switching frequency is recommended for the operation of multilevel inverters (MLIs) to achieve reduced switching losses. Selective harmonic elimination (SHE) and total harmonic distortion (THD) minimization are the two primary switching angle estimation methodologies for low-frequency modulation control. In this regard, a new generalized condition has been developed in this paper for the SHE technique. This original condition will give an output voltage with improved THD in comparison to the conventional SHE technique, while achieving its primary objective of eliminating the specific harmonic content from the output voltage. The proposed condition has been formulated by estimating the error associated with the staircase waveform and the desired sinusoidal output at the fundamental frequency. An infinite harmonic count has been considered for the evaluation of the quality of output, to obtain an accurate THD value without any underestimation. The proposed technique is analyzed, and its critical features are studied in Simulink. The effectiveness of the present work has been also validated by the experimental results.