Krishna Kumar Gupta

Dr. Krishna Kumar Gupta

Electrical and Instrumentation Engineering Department, Thapar Institute of Engineering and Technology, Patiala 147001 (Punjab), India

Research Focus & Metrics

Academic Career Length

8Years (2019-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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21 September 2020 in IEEE Journal of Emerging and Selected Topics in Power Electronics
Verified
Journal Article
Closed access
NSNagendra Singh
Nagendra Singh
Krishna Kumar GuptaKrishna Kumar Gupta
Krishna Kumar Gupta
SJSanjay K. Jain
Sanjay K. Jain
NDNiraj Dewangan
Niraj Dewangan
PALLAVEE BHATNAGARPALLAVEE BHATNAGAR
PALLAVEE BHATNAGAR
Large-scale solar photovoltaic (PV) systems encounter unpredictable partial shaded conditions (PSC). PSC, causing multiple peaks in the power-voltage (P–V) characteristics, potentially downgrades the performance of the PV system. However, the PV system should be operated at global maximum power point (GMPP) for its efficient utilization. For the tracking of GMPP, a scheme based on Flying Squirrel Search Optimization (FSSO) is proposed in this work. For an effective adoption with much reduced convergence time, the original FSSO is modified to update the squirrel position without the presence of predator. An experimental investigation of the proposed scheme is carried out employing a quasi-Z-source converter for the extraction of maximum power under PSC. The proposed scheme yields higher tracking efficiency, non-oscillatory steadystate response, and lower transients. Simulation and experimental investigations under various shading patterns indicate that the proposed strategy outperforms other popular maximum power point tracking (MPPT) strategies based on Perturb & Observe (P&O), Particle Swarm Optimization (PSO), and Grey Wolf Optimization (GWO).

26 July 2021 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
PALLAVEE BHATNAGARPALLAVEE BHATNAGAR
PALLAVEE BHATNAGAR
ASAnkit Kumar Singh
Ankit Kumar Singh
Krishna Kumar GuptaKrishna Kumar Gupta
Krishna Kumar Gupta
YSYam P. Siwakoti
Yam P. Siwakoti
The merit of switched-capacitors-based multilevel inverters (SCMLIs) is generally quantified in terms of a “cost function” (CF) that incorporates parameters such as voltage gain, component count, total standing voltage (TSV), and number of levels. In this article, a 13-level inverter is proposed with the aim of achieving a low value of CF. The proposed single-stage SCMLI uses one input source and three capacitors to attain a voltage gain of 3. It requires 13 power switches, of which the peak inverse voltage (PIV) of nine switches is restricted to the source voltage. The remaining four switches have PIV equal to twice the source voltage and they operate at low frequency. Thus, for all switches, the PIV is less than the amplitude of the output voltage. Moreover, the capacitors are self-balanced at all regions of modulation index values. The proposed inverter is validated through simulation and experimental results. A comparison of the proposed topology with other contemporary SCMLIs shows that it is highly competent in terms of CF, PIV and TSV requirements, waveform resolution, and capability to achieve voltage balancing of capacitors at low values of modulation index.

22 November 2019 in IEEE Journal of Emerging and Selected Topics in Power Electronics
Verified
Journal Article
Closed access
ACANILKUMAR CHAPPA
ANILKUMAR CHAPPA
SGShubhrata Gupta
Shubhrata Gupta
LSLalit Kumar Sahu
Lalit Kumar Sahu
SGShivam Gautam
Shivam Gautam
Krishna Kumar GuptaKrishna Kumar Gupta
Krishna Kumar Gupta
This paper presents a single-phase symmetrical and asymmetrical multilevel inverter (MLI) topology. The presented topology can generate 9-level output voltage in a symmetrical configuration, 13-level and 17-level in asymmetrical configuration with a single cell. The number of output levels can be improved further by increasing either the number of cells or switches in a single cell. The presented topology contains the least number of DC sources, semiconductor switches, capacitors and diodes as compared to classical and recently proposed topologies. Reduction in component count decreases the size, complexity and cost of the overall converter. A detailed comparison has been done of the presented topology with recently proposed topologies in terms of DC sources, semiconductor switches, capacitor and total blocking voltage. Finally, to validate the presented concept, the prototype of the presented nine-level. Thirteen-level and seventeen-level MLI topologies have been tested in the laboratory for different switching frequencies, different modulation indexes, sudden load changes and nonlinear load.

1 June 2020 in IEEE Transactions on Transportation Electrification
Verified
Journal Article
Closed access
ASAnkit Kumar Singh
Ankit Kumar Singh
AMAnjanee Kumar Mishra
Anjanee Kumar Mishra
Krishna Kumar GuptaKrishna Kumar Gupta
Krishna Kumar Gupta
PALLAVEE BHATNAGARPALLAVEE BHATNAGAR
PALLAVEE BHATNAGAR
TKTaehyung Kim
Taehyung Kim
A novel integrated converter for electric vehicles (EVs) is proposed in this work. For battery charging operation, the proposed converter system enables a complementary deployment of the utility grid and a solar photovoltaic (PV) system. Since both sources (acting one at a time) utilize the same converter, the developed charging system therefore has a smaller number of components. In addition, an inductor voltage detection (IVD) technique has been incorporated to correct the power factor in continuous conduction mode (CCM), which eliminates the need for a current sensor for power factor correction (PFC). The proposed system operates for all the modes required for an EV e.g., charging, propulsion (PRN) and regenerative braking (RBG). In charging mode (with either grid or solar PV), the proposed system operates as an isolated secondary ended primary inductance converter (SEPIC) converter. In PRN and RBG modes, it operates as a boost converter and a buck converter, respectively. Details of all these modes are described in the paper, along with the design of the components. In addition, results of simulation and experimental studies are presented for a 1 kW set-up based on the proposed configuration. A comparison with other topologies shows the techno-economic competence of the proposed system.

23 June 2022 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
AJAnekant Jain
Anekant Jain
Krishna Kumar GuptaKrishna Kumar Gupta
Krishna Kumar Gupta
SJSanjay K. Jain
Sanjay K. Jain
PALLAVEE BHATNAGARPALLAVEE BHATNAGAR
PALLAVEE BHATNAGAR
AC-to-DC conversion is integral to the two-stage charging interface of electric vehicle (EV) batteries. For such chargers, the use of multilevel rectifiers (MLRs) reduces voltage ratings of power switches, while achieving a high-quality input voltage waveform. Balancing of capacitors in MLRs, however, is an important challenge. In this work, a power factor correction (PFC) five-level rectifier with self-balanced switched capacitors is proposed. Each leg of the presented topology comprises five power switches and one switched capacitor, where the voltage ratings of power switches are equal to the output dc voltage. It does not require an additional filter capacitor on the dc side, as the load appears in parallel always with a switched capacitor of one of the legs. The five-level operation with continuous conduction leads to the elimination of the capacitive filter on the ac-side and inductive filter on the dc-side. This article presents the operating principle, modulation strategy, closed-loop control, and design aspects of the proposed rectifier. The proposed topology is validated through experimental results and a comparison is made with other topologies. Following three features of the proposed topology make it suitable for EV battery charging applications—buck operation with a wide output regulation, the possibility of bidirectional flow of power needed for vehicle-to-grid systems, and easy realization of its three-phase version by simply adding one more leg. These features too have been demonstrated with experimental results.

20 May 2020 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
ACANILKUMAR CHAPPA
ANILKUMAR CHAPPA
SGShubhrata Gupta
Shubhrata Gupta
LSLalit Kumar Sahu
Lalit Kumar Sahu
Krishna Kumar GuptaKrishna Kumar Gupta
Krishna Kumar Gupta
Low reliability is one of the significant worries of multilevel inverter (MLI) and which results due to the presence of higher number of switches and capacitors as compared to the conventional two-level inverter. Consequently, Fault-tolerant (FT) operation of MLI has attracted significant research attention. Therefore, in this paper, a nine-level inverter topology with FT characteristics is discussed. The proposed topology is capable of tolerating short circuit (SC) and open circuit (OC) faults not only in the single switch but also in multiple switches. It preserves output power, voltage levels and capacitor voltage balancing under pre and post fault operation. The proposed MLI topology requires least number of DC sources, capacitors, switches, clamping diodes and total blocking voltage in comparison to recently proposed topologies. Thus, offering better efficiency profile under pre and post fault conditions. The proposed work has been validated experimentally with a laboratory prototype.