Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and 2 $\times$ 1 mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density Y $_{\text{2}}$ O $_{\text{3}}$ -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

Here, we report an implementation of ( $8\times8$ ) $\text{Y}_{{2}}\text{O}_{{3}}$ -based memristive crossbar array (MCA) out of a total dimension of ( $30\times25$ ) array fabricated by utilizing a dual ion beam sputtering (DIBS) system. The selected ( $8\times8$ ) MCA is further used to electrically write random alphabets and perform synaptic learning characteristics to perform analog and neuromorphic computing applications. The MCA effectively exhibits multiple current levels and mimics various artificial synaptic properties with superior bidirectional switching responses. The MCA mimics potentiation, depression, and different Hebbian learning-based spike-time-dependent plasticity rules, suggesting the importance of the $\text{Y}_{{2}}\text{O}_{{3}}$ -based MCA for large-scale neuromorphic and analog computations. This work provides different insights into the design of an artificial synapse by utilizing $\text{Y}_{{2}}\text{O}_{{3}}$ as a switching oxide in memristors.

Here, we report the electrical performance analysis of a Y ₂ O ₃ -based memristive crossbar array (MCA) of ( $30\,{\times }\,25$ ) on a large Si (100) wafer having a 3-inch diameter by utilizing dual-ion beam sputtering (DIBS) system. The MCA is highly stable and exhibits repeatable and reproducible resistive switching responses in terms of consistent resistive switching voltages ( ${V}_{{\mathrm {SET}}}$ and ${V}_{{\mathrm {RESET}}}$ ). The devices in the MCA efficiently depict the impact of device area scaling on the switching voltage parameters. The fabricated devices also show low device-to-device (D2D) variability in ${V}_{{\mathrm {SET}}}$ (2.64%) ${V}_{{\mathrm {RESET}}}$ (10.13%) and ultralow cycle-to-cycle (C2C) variability in ${V}_{{\mathrm {SET}}}$ (0.2%) and ${V}_{{\mathrm {RESET}}}$ (1.07%). Furthermore, this work also experimentally probes the impacts of various input signal parameters such as applied voltage, compliance current, and pulsewidth (PW) on the variability parameters.

In this article, the effect of the SiO2 layer is demonstrated on Dual ion beam sputtered yttria-based memristive devices for the first time. It is found that the effect of thickening of SiO2 layer is extremely detrimental for resistive switching (RS) parameters such as endurance and uniformity of current-voltage characteristics. SiO2 interfacial layer causes the growth of nano stalagmite in the yttria layer. This interfacial layer is also responsible for the origin of pseudo bipolarity in RS characteristics and early failure of the device during endurance testing. The thickness of the SiO2 layer has a positive correlation with deposition temperature and oxygen partial pressure. It is found that the deposition temperature of 300°C and a mixture of Ar: O2 with a ratio of 2:3 shows the best RS characteristics.

Here, we report the detailed fabrication and electrical analysis of atomic layer deposited single (i.e., HfO2) and bilayer (i.e., HfO2/Ta2O5)-based memristive devices. The bilayer devices show stable retention properties $\gt 10^{{3}}$ s with an improved on/off ratio. Moreover, the bilayer devices also exhibit higher change in the device resistance (25%–30%) as compared to resistance change (~12%) in single-layer devices under the same electrical programming scheme. The least values of coefficient of variability ( ${C} _{\text {V}}$ ) in cycle-to-cycle (C2C) in the device resistance states are 0.19% low-resistance state (LRS) and 0.28% high-resistance state (HRS) for single-layer device, while in the case of bilayer devices, these values are 1.10% (LRS) and 0.29% (HRS). Furthermore, the impedance spectroscopy (EIS) analysis reveals that the switching mechanism is more dominant due to the change in the device resistance rather than the device capacitance. Therefore, this work opens a new way to further explore the ac analysis of memristive devices and their potential applications in various fields.