In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

Sweep frequency response analysis (SFRA) is a diagnostic technique which can identify faults within transformers. Though SFRA approaches are used to identify faults, their effectiveness in discriminating two same level faults at two different locations within transformer is not much analysed and reported. Experiments were carried out on a 1 kVA, single phase, 240 V/240 V laboratory transformers and on a 315 kVA, three phase, 11 kV/433 V, Dyn11, ONAN, distribution transformer, to analyse the usefulness of SFRA in inter turn short identification and discriminations. Faulty conditions were created artificially in transformers, by shorting the tappings provided in one of their windings, at different levels and locations. Open circuit self‐impedance and transfer voltage transfer function approaches were experimented and transfer function plots representing winding impedance and voltage transfer ratios at various frequencies were developed for transformers, under normal and faulty conditions. Significant differences were identified at some frequencies while comparing normal case plots with faulty case plots. It was observed that the SFRA is effective in identifying shorts within transformer winding as well as, discriminating two same level shorts (i.e.) locating shorts. Statistical analysis using absolute difference and min–max ratio also confirmed the efficacy of these approaches.

This paper, proposed a hybrid full adder with low power and less area using 8 transistors. Majority not gate and GDI techniques are collectively used for design this hybrid full adder. Some beforehand composed cells endure from non-full swing output, low speed, and high power utilization issues. While the new full adder has insignificant range overhead, it has enhanced the power Utilization of the circuit when contrasted with other full adder circuit. We have verified this full adder by utilizing cadence virtuoso gpdk 180nm technology at 1.2V supply voltage.

This paper presents the simulation based design of analog integrated circuit design using an evolutionary algorithm. We design a basic two stage opamp using multi objective optimization based techniques, namely particle swarm optimization and non-dominated sorting genetic algorithm. These two algorithms are new kind of multi objective optimization method used to design analog IC transistor sizes and biasing currents. The necessities of these algorithms are to reduce the circuit design time and improve the accuracy of performance parameters. In this work, we automatically synthesize transistor sizes with constraint function using PSO and NSGA-II.

Wireless sensor networks find applications everywhere in day to day activities right from attendance entry systems to healthcare monitoring systems. The evolution of the Internet of Things (IoT) as the Internet of Everything (IoET) makes the wireless sensor network omnipresent and increases the use of Radio Frequency Identification (RFID) for the proper identification of devices and sensor nodes which are mostly battery operated. As technology evolves, security threats also increase rapidly. This mandates a strong and energy-efficient green solution. This work attempted to address these issues by effectively deploying the lightweight encryption scheme called Extended Tiny Encryption Algorithm (XTEA). Though the XTEA is lightweight and famous, it is commonly known for various attacks. Our work patches the security threats in the XTEA by applying domain-specific customization, random number utilization, and undisclosed key renewal techniques. Two custom Renovated XTEA Mutual Authentication Protocol (RXMAP) encoder architectures, namely, RXMAP-1 and RXMAP-2, are proposed based on the replacement of accurate computational blocks with approximate blocks. The proposed RXMAP protocol is evaluated for its computational and storage overhead and verified against various security threats using BAN logic formal verification and informal verification. The proposed encoder architectures are simulated for functional verification, and ASIC implementation is done with a 132nm process node. ASIC implementation results show that the proposed designs RXMAP-1 and RXMAP-2 occupy 53.11 and 53.31 lesser area compared to XTEA I and 52.97 and 53.18 lesser area compared to XTEA II implementation. The total power consumed by the proposed encoder architectures RXMAP-1 and RXMAP-2 is 68.76 and 71.64 lesser than XTEA II implementation, respectively, while maintaining the equal throughput.

Oral dosage forms are the most widely employed method of drug delivery in therapeutic treatments. However, the presence of visual defects in blister packages can adversely affect the drug's bioavailability and therapeutic efficacy, potentially compromising treatment outcomes. Consequently, detecting tablet defects post-blister packaging in real-time represents a critical challenge in the pharmaceutical industry. Additionally, factors such as blister reflections and limited dataset size hinder the deep learning model's ability to identify defects accurately. To address these challenges, the PharmaNet deep model is developed utilizing a convolutional neural network (CNN) architecture, incorporating defect-guided dynamic feature fusion (DGDFF) in which the fusion process is dynamically guided by potential defect regions, allowing the model to focus on relevant features (defect areas) more efficiently, adaptive deep chain (ADC) which includes occlusion pattern generator (OPG) and residual recursive feature reconstructor (R²FR). The OPG creates multiple views of potential defect regions by systematically dividing features into blocks and creating layered occlusions. At the same time, the R²FR uses gates with ELU activation and residual connections to reconstruct detailed features from these occluded sequences, ultimately enhancing the model's ability to detect subtle defects. The model culminates in an uncertainty-aware detection head that enhances defect prediction reliability by incorporating uncertainty estimates alongside traditional class probabilities and bounding box predictions. This provides a more informed and interpretable decision-making process for pharmaceutical quality control in real-time. Empirical evaluation on the proposed model demonstrates state-of-the-art performance with 99.4% mAP on the PharmaBlister dataset and 97.2% mAP on MVTech AD, with minimal predictive uncertainty, validating its efficacy in pharmaceutical quality control applications.