Modern computer technology devices do not keep pace with the high growth rate of quantitative and qualitative characteristics of digital images. The computational complexity of the wavelet transform must be reduced for the hardware-friendly implementation of wavelet image processing methods on microelectronic devices. This paper proposes a new approach to reduce the computational complexity of wavelet image processing based on the Winograd method. Group pixel processing using Winograd method reduces the asymptotic computational complexity by up to 72.9% compared to the traditional pixel-by-pixel processing approach, according to the results obtained. A theoretical evaluation of the resource costs of a wavelet image processing device based on the unit-gate model showed that Winograd method reduces device delay to 73.62% and device area to 34.03% compared to the direct implementation. The greatest reduction in resource costs is observed mainly when obtaining fragments of the processed image with 5 pixels. At the same time, the greatest rate of resource reduction is observed when obtaining fragments of the processed image with 3 pixels. Further increase in the fragments size leads to a significantly smaller reduction in resource costs while increasing the complexity of circuits design. Separation of filters into several components is more hardware-friendly when using high-order wavelets. Verification of all obtained results on field-programmable gate arrays and application-specific integrated circuits is a promising direction for further research.

Matrix multiplication is a commonly used operation in various graphics, imaging, robotics, and signal processing applications. In connection with the increase in the growth of the characteristics of digital information, it is necessary to improve the algorithms for processing information and the efficiency of their implementation. Various fast matrix multiplication algorithms are used to solve this problem. This paper presents a comparative analysis of the computational complexity of matrix multiplication implemented using the direct, Strassen and Coopersmith-Winograd algorithms. A theoretical analysis showed that the use of fast matrix multiplication algorithms can reduce the delay and area compared to the direct algorithm to 82.68% and 5.03%, respectively, depending on the selected adder, matrix multiplication algorithm and matrix size. In further research, it is planned to implement matrix multiplication hardware using the Strassen and Coopersmith-Winograd algorithms on FPGA and ASIC, and their comparative analysis.

Wavelets are actively used to solve a wide range of image processing problems in various fields of science and technology. Modern image processing systems cannot keep up with the rapid growth in digital visual information. Various approaches are used to reduce the computational complexity and increase computational speeds. The Winograd method (WM) is one of the most promising. However, this method is used to obtain sequential values. Its use for wavelet image processing requires expanding the calculation methodology to cases of downsampling. This paper proposes a new approach to reduce the computational complexity of wavelet image processing based on the WM with decimation. Calculations have been carried out and formulas have been derived that implement digital filtering using the WM with downsampling. The derived formulas can be used for 1D filtering with an arbitrary downsampling stride. Hardware modeling of wavelet image filtering on an FPGA showed that the WM reduces the computational time by up to 66%, with increases in the hardware costs and power consumption of 95% and 344%, respectively, compared to the direct method. A promising direction for further research is the implementation of the developed approach on ASIC and the use of modular computing for more efficient parallelization of calculations and an even greater increase in the device speed.

In this paper, we propose an approach for finding balanced special-type sets of moduli for high-speed digital signal filtering using the residue number system and utilizing the truncated multiply-accumulate blocks. The primary focus is to conduct a thorough analysis of the computational delay associated with individual residue number system moduli sets as well as their various combinations. Our proposed approach reduces the digital filtering delay by 60.85% depending on the computational range and bit-width of residue number system moduli for 16-, 24-, 32-, and 48-bit filters. The proposed approach can significantly enhance the performance of digital devices where data processing speed is critical. Further research will explore applying these filters to tackle various challenges in both digital signal and image processing.