Medical imaging using different modalities has many problems. The main ones are low informativeness, various distortion noises, and a large amount of information. Fusion, denoising, and visual data compression are used to solve them in practice. Discrete wavelet transform is one way to implement various fusion, denoising, and compression methods for 2D and 3D medical image processing. Medical imaging systems produce increasingly accurate images with scanning technology and digital devices development. These images have improved quality using both higher spatial resolutions and color bit-depth. Processing a large volume of medical imaging data requires considerable resources and processing time. Modern wavelet-based devices for medical image processing do not meet the current performance demand. Hardware accelerators are being designed to solve this problem. This paper proposes new (field-programmable gate array) FPGA accelerators using wavelet processing (WP) with scaled filter coefficients (SFC) and parallel computing in residue number system (RNS) to improve the performance of high-quality 3D medical image WP systems. The computational complexity is reduced using the developed WP method with SFC and the proposed wavelet filter coefficients scaling algorithm. Parallel computing is organized in RNS using moduli sets of a particular type. Hardware implementation of 3D medical image WP using the proposed FPGA accelerators increases device performance by 2.89-3.59 times, increasing the hardware resources by 1.18-3.29 times compared to state-of-the-art solutions. The device performance improvement is achieved while maintaining high-quality 3D medical image processing in peak signal-to-noise ratio terms.

Matrix multiplication is a commonly used operation in various graphics, imaging, robotics, and signal processing applications. In connection with the increase in the growth of the characteristics of digital information, it is necessary to improve the algorithms for processing information and the efficiency of their implementation. Various fast matrix multiplication algorithms are used to solve this problem. This paper presents a comparative analysis of the computational complexity of matrix multiplication implemented using the direct, Strassen and Coopersmith-Winograd algorithms. A theoretical analysis showed that the use of fast matrix multiplication algorithms can reduce the delay and area compared to the direct algorithm to 82.68% and 5.03%, respectively, depending on the selected adder, matrix multiplication algorithm and matrix size. In further research, it is planned to implement matrix multiplication hardware using the Strassen and Coopersmith-Winograd algorithms on FPGA and ASIC, and their comparative analysis.